From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 17 Aug 2015 09:35:44 -0400 Subject: [U-Boot] [PATCH 3/3] ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 In-Reply-To: <1439477460-25544-4-git-send-email-nm@ti.com> References: <1439477460-25544-1-git-send-email-nm@ti.com> <1439477460-25544-4-git-send-email-nm@ti.com> Message-ID: <20150817133544.GE25532@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Aug 13, 2015 at 09:51:00AM -0500, Nishanth Menon wrote: > DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet > provided IODELAY values for standard RGMII phys do not work. > > Silicon Revision(SR) 2.0 provides an alternative bit configuration > that allows us to do a "gross adjustment" to launch the data off a > different internal clock edge. Manual IO Delay overrides are still > necessary to fine tune the clock-to-data delays. This is a necessary > workaround for the quirky ethernet Phy we have on the platform. > > NOTE: SMA registers are spare "kitchen sink" registers that does > contain bits for other workaround as necessary as well. Hence the > control for the same is introduced in a generic SoC specific, board > generic location. > > Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: