From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 20 Aug 2015 05:46:13 +0200 Subject: [U-Boot] [v3 1/4] spi: cadence_qspi: move trigger base configuration in init In-Reply-To: <1439604960-23919-2-git-send-email-vikas.manocha@st.com> References: <1439604960-23919-1-git-send-email-vikas.manocha@st.com> <1439604960-23919-2-git-send-email-vikas.manocha@st.com> Message-ID: <201508200546.13318.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Saturday, August 15, 2015 at 04:15:57 AM, Vikas Manocha wrote: > No need to configure indirect trigger address for every read/write. > > Signed-off-by: Vikas Manocha > --- > > Changes in v3: added commit message & removed extra bracket. > Changes in v2: Rebased to master > > drivers/spi/cadence_qspi_apb.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c > b/drivers/spi/cadence_qspi_apb.c index d053407..b46e5fe 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct > cadence_spi_platdata *plat) > > /* Indirect mode configurations */ > writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); > + writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK, > + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); Please drop this (u32) cast, it's misleading and problematic. Best regards, Marek Vasut