From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel
Date: Fri, 21 Aug 2015 02:42:16 +0200 [thread overview]
Message-ID: <201508210242.16444.marex@denx.de> (raw)
In-Reply-To: <55D671F4.8040706@opensource.altera.com>
On Friday, August 21, 2015 at 02:33:56 AM, Dinh Nguyen wrote:
> On 8/20/15 4:59 PM, Marek Vasut wrote:
> > On Thursday, August 20, 2015 at 11:55:02 PM, Dinh Nguyen wrote:
> >> +CC: Simon Glass
> >
> > Hi Dinh,
> >
> >> On Thu, Aug 20, 2015 at 12:32 AM, Marek Vasut <marex@denx.de> wrote:
> >>> On Thursday, August 20, 2015 at 07:28:02 AM, Chin Liang See wrote:
> >>>> Hi,
> >>>>
> >>>> On Wed, 2015-08-19 at 14:36 +0000, marex at denx.de wrote:
> >>>>> On Wednesday, August 19, 2015 at 10:21:17 AM, Chin Liang See wrote:
> >>>>>> Hi,
> >>>>>
> >>>>> Hi again,
> >>>>>
> >>>>>> On Wed, 2015-08-19 at 02:41 +0000, marex at denx.de wrote:
> >>>>>>> On Wednesday, August 19, 2015 at 07:54:50 AM, Chin Liang See wrote:
> >>>>>>>> Enable SDMMC calibration to determine the best setting for
> >>>>>>>> drvsel and smpsel. It will be triggered whenever there is
> >>>>>>>> a change of card frequency and bus width. This is to ensure
> >>>>>>>> reliable transmission between the controller and the card.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
> >>>>>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> >>
> >> I think there's something wrong with your git scripts, I did not get
> >> this email.
> >
> > You're not getting quite a lot of email I think. Could it be that altera
> > has some issues with their mail system after some 300 patches went
> > through your mailbox ? You sure you're not being filtered ? :b
>
> I would not be surprised if I was, but I don't think I am. Since I
> explicitly included my email address in the CC line on my earlier
> response, I am seeing the mail just fine now. My opensource.altera.com
> address was not even in the cc address line at all in any of the earlier
> emails.
Oh, I see, thank you for clarifying :)
Could it be that the ML itself is behaving in a funny way ? I saw this a
few times before too.
btw did you get my email about the IOCSR ?
Best regards,
Marek Vasut
next prev parent reply other threads:[~2015-08-21 0:42 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-19 5:54 [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel Chin Liang See
2015-08-19 7:26 ` Pavel Machek
2015-08-19 7:34 ` Marek Vasut
2015-08-19 8:30 ` Chin Liang See
2015-08-19 23:23 ` Marek Vasut
2015-08-19 8:33 ` Chin Liang See
2015-08-19 7:40 ` Marek Vasut
2015-08-19 8:21 ` Chin Liang See
2015-08-19 19:36 ` Marek Vasut
2015-08-20 5:28 ` Chin Liang See
2015-08-20 5:32 ` Marek Vasut
2015-08-20 21:55 ` Dinh Nguyen
2015-08-20 21:59 ` Marek Vasut
2015-08-21 0:33 ` Dinh Nguyen
2015-08-21 0:42 ` Marek Vasut [this message]
2015-08-21 20:52 ` Simon Glass
2015-08-24 15:04 ` Chin Liang See
2015-08-25 2:36 ` Jaehoon Chung
2015-08-25 3:08 ` Chin Liang See
2015-08-26 5:29 ` Jaehoon Chung
2015-08-26 5:47 ` Chin Liang See
2015-08-26 6:14 ` Jaehoon Chung
2015-08-26 6:54 ` Chin Liang See
2015-09-01 8:54 ` Chin Liang See
2015-09-01 9:01 ` Marek Vasut
2015-09-01 9:10 ` Chin Liang See
2015-09-01 10:12 ` Jaehoon Chung
2015-09-01 14:53 ` Dinh Nguyen
2015-09-02 10:32 ` Marek Vasut
2015-09-03 0:27 ` Chin Liang See
2015-09-03 5:30 ` Jaehoon Chung
2015-09-03 9:37 ` Marek Vasut
2015-09-03 14:06 ` Chin Liang See
2015-09-03 14:25 ` Marek Vasut
2015-09-04 10:41 ` Pavel Machek
2015-09-07 8:33 ` Jaehoon Chung
2015-09-08 1:32 ` Chin Liang See
2015-09-08 10:56 ` Marek Vasut
[not found] ` <0016CF5815A1B142902817051AF62EB305FDF5BA@PG-ITEXCH01.altera.priv.altera.com>
2015-10-07 2:54 ` Chin Liang See
2015-10-12 14:44 ` Marek Vasut
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