From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 25 Aug 2015 22:13:54 +0200
Subject: [U-Boot] [RESEND PATCH v4 0/5] spi: cadence_qspi: optimize &
	fix indirect rd-writes
In-Reply-To: <1440531934-32652-1-git-send-email-vikas.manocha@st.com>
References: <1440531934-32652-1-git-send-email-vikas.manocha@st.com>
Message-ID: <201508252213.54647.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Tuesday, August 25, 2015 at 09:45:29 PM, Vikas Manocha wrote:
> This patchset:
> - fixes trigger base & transfer start address register programming. This
> fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb
> trigger address setting".
> - adds support to get fifo width from device tree
> 
> Changes in v4:
> - fifo-width & trigger address alligned to linux device tree binding.
> - renaming of one parameter splitted to separate patch.
> - trigger address of socfpga reverted back to 0x0.
> - code formatting done to avoid checkpatch CHECKS.

OK, this is obviously not 1:1 resend. The previous patchset had at least
a different cover letter. So is this a V5 or what is this really ? Please
do not tag "RESEND" stuff which actually contain modifications, this sort
of behavior is absolutelly not helpful.

Best regards,
Marek Vasut