[U-Boot] [RESEND PATCH v4 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes

[Marek Vasut <marex@denx.de>]

On Tuesday, August 25, 2015 at 10:56:17 PM, vikas wrote:
> Hi,
> 
> On 08/25/2015 01:13 PM, Marek Vasut wrote:
> > On Tuesday, August 25, 2015 at 09:45:29 PM, Vikas Manocha wrote:
> >> This patchset:
> >> - fixes trigger base & transfer start address register programming. This
> >> fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect
> >> ahb trigger address setting".
> >> - adds support to get fifo width from device tree
> >> 
> >> Changes in v4:
> >> - fifo-width & trigger address alligned to linux device tree binding.
> >> - renaming of one parameter splitted to separate patch.
> >> - trigger address of socfpga reverted back to 0x0.
> >> - code formatting done to avoid checkpatch CHECKS.
> > 
> > OK, this is obviously not 1:1 resend. The previous patchset had at least
> > a different cover letter. So is this a V5 or what is this really ? Please
> > do not tag "RESEND" stuff which actually contain modifications, this sort
> > of behavior is absolutelly not helpful.
> 
> The intention of quick "RESEND v4" was for reviewers to ignore v4 to save
> their time. Let me know if i need to mark it v5.

Yes, it was supposed to be marked as V5 if it contained changes.

Best regards,
Marek Vasut