From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 26 Aug 2015 15:38:14 +0200
Subject: [U-Boot] [PATCH] spi: cadence_qspi: Enable quad mode for read
	and programming
In-Reply-To: <CAPnjgZ3oKX3Td1y5Yvhk3zhnF2-2fv3frRPHrsB-WASMi3_GFA@mail.gmail.com>
References: <1440547795-2077-1-git-send-email-clsee@altera.com>
 <201508260857.11280.marex@denx.de>
 <CAPnjgZ3oKX3Td1y5Yvhk3zhnF2-2fv3frRPHrsB-WASMi3_GFA@mail.gmail.com>
Message-ID: <201508261538.14272.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Wednesday, August 26, 2015 at 03:19:21 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 25 August 2015 at 23:57, Marek Vasut <marex@denx.de> wrote:
> > On Wednesday, August 26, 2015 at 02:09:55 AM, Chin Liang See wrote:
> >> Enable the quad output fast read and quad input fast program
> >> support. Quad mode is supported by Cadence QSPI controller.
> >> 
> >> Signed-off-by: Chin Liang See <clsee@altera.com>
> >> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> >> Cc: Stefan Roese <sr@denx.de>
> >> Cc: Vikas Manocha <vikas.manocha@st.com>
> >> Cc: Jagannadh Teki <jteki@openedev.com>
> >> Cc: Pavel Machek <pavel@denx.de>
> >> Cc: Marek Vasut <marex@denx.de>
> >> ---
> >> 
> >>  drivers/spi/cadence_qspi.c     |   11 +++++++++++
> >>  drivers/spi/cadence_qspi_apb.c |   16 ++++++++++++----
> >>  2 files changed, 23 insertions(+), 4 deletions(-)
> >> 
> >> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> >> index 34a0f46..c6b69c4 100644
> >> --- a/drivers/spi/cadence_qspi.c
> >> +++ b/drivers/spi/cadence_qspi.c
> >> @@ -318,6 +318,16 @@ static int cadence_spi_ofdata_to_platdata(struct
> >> udevice *bus) return 0;
> >> 
> >>  }
> >> 
> >> +static int cadence_spi_child_pre_probe(struct udevice *dev)
> >> +{
> >> +     struct spi_slave *slave = dev_get_parentdata(dev);
> >> +
> >> +     /* Cadence QSPI controller can support quad read and program */
> >> +     slave->op_mode_rx = SPI_OPM_RX_QOF;
> >> +     slave->op_mode_tx = SPI_OPM_TX_QPP;
> >> +     return 0;
> >> +}
> >> +
> >> 
> >>  static const struct dm_spi_ops cadence_spi_ops = {
> >>  
> >>       .xfer           = cadence_spi_xfer,
> >>       .set_speed      = cadence_spi_set_speed,
> >> 
> >> @@ -341,5 +351,6 @@ U_BOOT_DRIVER(cadence_spi) = {
> >> 
> >>       .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
> >>       .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
> >>       .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
> >> 
> >> +     .child_pre_probe = cadence_spi_child_pre_probe,
> >> 
> >>       .probe = cadence_spi_probe,
> >>  
> >>  };
> > 
> > Simon, can you please check if this DM bit is correct ?
> 
> It seems OK to me. I worry a bit that xfer() is causing SPI controller
> changes to happen based on inspection of the bytes being sent. I think
> that is what Marek is saying below. Do we need a new method for SPI to
> set the protocol?

Yes, that's what I'm saying.

> The license header in cadence_qspi_apb.c should move to SPDX.
> 
> For the driver model bits:
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>

Thanks :)