* [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
@ 2015-09-02 9:10 Stefan Roese
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Stefan Roese @ 2015-09-02 9:10 UTC (permalink / raw)
To: u-boot
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
And use the command "nandecc bch4" to select this ECC scheme upon runtime.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/mtd/nand/fsmc_nand.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 567eff0..19f5526 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/mtd/nand_bch.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
@@ -390,6 +391,45 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
return 0;
}
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsmc_nand_switch_ecc - switch the ECC operation between different engines
+ *
+ * @eccstrength - the number of bits that could be corrected
+ * (1 - HW, 4 - SW BCH4)
+ */
+int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ int err = 0;
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ /* Setup the ecc configurations again */
+ if (eccstrength == 1) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.bytes = 3;
+ nand->ecc.strength = 1;
+ nand->ecc.layout = &fsmc_ecc1_layout;
+ nand->ecc.correct = nand_correct_data;
+ } else {
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+ nand->ecc.calculate = nand_bch_calculate_ecc;
+ nand->ecc.correct = nand_bch_correct_data;
+ nand->ecc.bytes = 7;
+ nand->ecc.strength = 4;
+ nand->ecc.layout = NULL;
+ }
+
+ /* Update NAND handling after ECC mode switch */
+ err = nand_scan_tail(mtd);
+
+ return err;
+}
+#endif /* CONFIG_SPL_BUILD */
+
int fsmc_nand_init(struct nand_chip *nand)
{
static int chip_nr;
--
2.5.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
2015-09-02 9:10 [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
@ 2015-09-02 9:10 ` Stefan Roese
2015-09-02 11:15 ` Viresh Kumar
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
2015-09-02 9:10 ` [U-Boot] [PATCH 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board Stefan Roese
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Stefan Roese @ 2015-09-02 9:10 UTC (permalink / raw)
To: u-boot
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 34 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-spear/spr_misc.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index e39cdba..be0d14f 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -83,3 +83,37 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ /* 1-bit HW ECC */
+ printf("Switching to 1-bit HW ECC\n");
+ fsmc_nand_switch_ecc(1);
+ } else if (strncmp(argv[1], "bch4", 2) == 0) {
+ /* 4-bit SW ECC BCH4 */
+ printf("Switching to 4-bit SW ECC (BCH4)\n");
+ fsmc_nand_switch_ecc(4);
+ } else {
+ goto usage;
+ }
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 0, do_switch_ecc,
+ "switch NAND ECC calculation algorithm",
+ "hw|bch4 - Switch between NAND hardware 1-bit HW and"
+ " 4-bit SW BCH\n"
+);
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index b55026e..6f2e19e 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -253,5 +253,6 @@ struct misc_regs {
#define SOC_SPEAR320 203
extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif
--
2.5.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board
2015-09-02 9:10 [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
@ 2015-09-02 9:10 ` Stefan Roese
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
2015-09-02 9:11 ` [U-Boot] [PATCH 4/4] arm: spear: Enable THUMB mode on " Stefan Roese
2015-09-02 11:13 ` [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Viresh Kumar
3 siblings, 1 reply; 9+ messages in thread
From: Stefan Roese @ 2015-09-02 9:10 UTC (permalink / raw)
To: u-boot
This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that
needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally.
This patch enables the SW 4-bit BCH support for this board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
---
include/configs/x600.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 6a57388..f672485 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -67,6 +67,8 @@
#define CONFIG_MTD_ECC_SOFT
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
/* UBI/UBI config options */
#define CONFIG_MTD_DEVICE
--
2.5.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 4/4] arm: spear: Enable THUMB mode on x600 board
2015-09-02 9:10 [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
2015-09-02 9:10 ` [U-Boot] [PATCH 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board Stefan Roese
@ 2015-09-02 9:11 ` Stefan Roese
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
2015-09-02 11:13 ` [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Viresh Kumar
3 siblings, 1 reply; 9+ messages in thread
From: Stefan Roese @ 2015-09-02 9:11 UTC (permalink / raw)
To: u-boot
To reduce the size of the U-Boot image on the x600 board, lets enable
the THUMB mode. This reduces the overall size to less than 0x6000
bytes. Fitting it again in the onboard NOR flash.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
---
include/configs/x600.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/x600.h b/include/configs/x600.h
index f672485..73ba67c 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -17,6 +17,7 @@
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_THUMB_BUILD
#include <asm/arch/hardware.h>
--
2.5.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
2015-09-02 9:10 [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
` (2 preceding siblings ...)
2015-09-02 9:11 ` [U-Boot] [PATCH 4/4] arm: spear: Enable THUMB mode on " Stefan Roese
@ 2015-09-02 11:13 ` Viresh Kumar
3 siblings, 0 replies; 9+ messages in thread
From: Viresh Kumar @ 2015-09-02 11:13 UTC (permalink / raw)
To: u-boot
On 02-09-15, 11:10, Stefan Roese wrote:
> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
> be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
> The SPEAr600 HW ECC only supports 1-bit ECC strength.
>
> To enable SW BCH4, you need to specify this in your config header:
>
> And use the command "nandecc bch4" to select this ECC scheme upon runtime.
>
> Tested on SPEAr600 x600 board.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Scott Wood <scottwood@freescale.com>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> drivers/mtd/nand/fsmc_nand.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 567eff0..19f5526 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -13,6 +13,7 @@
> #include <asm/io.h>
> #include <linux/bitops.h>
> #include <linux/err.h>
> +#include <linux/mtd/nand_bch.h>
> #include <linux/mtd/nand_ecc.h>
> #include <linux/mtd/fsmc_nand.h>
> #include <asm/arch/hardware.h>
> @@ -390,6 +391,45 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
> return 0;
> }
>
> +#ifndef CONFIG_SPL_BUILD
> +/*
> + * fsmc_nand_switch_ecc - switch the ECC operation between different engines
> + *
> + * @eccstrength - the number of bits that could be corrected
> + * (1 - HW, 4 - SW BCH4)
> + */
> +int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
> +{
> + struct nand_chip *nand;
> + struct mtd_info *mtd;
> + int err = 0;
You don't have to initialize it.
> +
> + mtd = &nand_info[nand_curr_device];
> + nand = mtd->priv;
> +
> + /* Setup the ecc configurations again */
> + if (eccstrength == 1) {
> + nand->ecc.mode = NAND_ECC_HW;
> + nand->ecc.bytes = 3;
> + nand->ecc.strength = 1;
> + nand->ecc.layout = &fsmc_ecc1_layout;
> + nand->ecc.correct = nand_correct_data;
> + } else {
> + nand->ecc.mode = NAND_ECC_SOFT_BCH;
> + nand->ecc.calculate = nand_bch_calculate_ecc;
> + nand->ecc.correct = nand_bch_correct_data;
> + nand->ecc.bytes = 7;
> + nand->ecc.strength = 4;
> + nand->ecc.layout = NULL;
> + }
> +
> + /* Update NAND handling after ECC mode switch */
> + err = nand_scan_tail(mtd);
> +
> + return err;
> +}
> +#endif /* CONFIG_SPL_BUILD */
> +
> int fsmc_nand_init(struct nand_chip *nand)
> {
> static int chip_nr;
Other than that:
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
@ 2015-09-02 11:15 ` Viresh Kumar
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Viresh Kumar @ 2015-09-02 11:15 UTC (permalink / raw)
To: u-boot
On 02-09-15, 11:10, Stefan Roese wrote:
> This patch adds the "nandecc" command to switch between the SPEAr600 internal
> 1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
> chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
> switch between both ECC schemes for backwards compatibility.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> arch/arm/cpu/arm926ejs/spear/cpu.c | 34 ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-spear/spr_misc.h | 1 +
> 2 files changed, 35 insertions(+)
For [2-4]/4:
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [U-Boot, 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
2015-09-02 11:15 ` Viresh Kumar
@ 2015-09-12 12:50 ` Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 11:10:58AM +0200, Stefan Roese wrote:
> This patch adds the "nandecc" command to switch between the SPEAr600 internal
> 1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
> chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
> switch between both ECC schemes for backwards compatibility.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [U-Boot, 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board
2015-09-02 9:10 ` [U-Boot] [PATCH 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board Stefan Roese
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 9+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 11:10:59AM +0200, Stefan Roese wrote:
> This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that
> needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally.
> This patch enables the SW 4-bit BCH support for this board.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [U-Boot, 4/4] arm: spear: Enable THUMB mode on x600 board
2015-09-02 9:11 ` [U-Boot] [PATCH 4/4] arm: spear: Enable THUMB mode on " Stefan Roese
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 9+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 11:11:00AM +0200, Stefan Roese wrote:
> To reduce the size of the U-Boot image on the x600 board, lets enable
> the THUMB mode. This reduces the overall size to less than 0x6000
> bytes. Fitting it again in the onboard NOR flash.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
Applied to u-boot/master, thanks!
--
Tom
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end of thread, other threads:[~2015-09-12 12:50 UTC | newest]
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2015-09-02 9:10 [U-Boot] [PATCH 1/4] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
2015-09-02 9:10 ` [U-Boot] [PATCH 2/4] arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4 Stefan Roese
2015-09-02 11:15 ` Viresh Kumar
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
2015-09-02 9:10 ` [U-Boot] [PATCH 3/4] arm: spear: Add BCH4 SW support to SPEAr600 x600 board Stefan Roese
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
2015-09-02 9:11 ` [U-Boot] [PATCH 4/4] arm: spear: Enable THUMB mode on " Stefan Roese
2015-09-12 12:50 ` [U-Boot] [U-Boot, " Tom Rini
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