* [U-Boot] [PATCH v2 1/9] powerpc: ppc4xx: remove alpr support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:58 ` [U-Boot] [U-Boot,v2,1/9] " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 2/9] powerpc: ppc4xx: remove csb272, csb472 support Masahiro Yamada
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/prodrive/alpr/Kconfig | 12 --
board/prodrive/alpr/MAINTAINERS | 6 -
board/prodrive/alpr/Makefile | 9 --
board/prodrive/alpr/alpr.c | 215 ------------------------
board/prodrive/alpr/config.mk | 16 --
board/prodrive/alpr/fpga.c | 239 ---------------------------
board/prodrive/alpr/init.S | 53 ------
board/prodrive/alpr/nand.c | 124 --------------
configs/alpr_defconfig | 7 -
doc/README.scrapyard | 3 +-
include/configs/alpr.h | 351 ----------------------------------------
12 files changed, 2 insertions(+), 1037 deletions(-)
delete mode 100644 board/prodrive/alpr/Kconfig
delete mode 100644 board/prodrive/alpr/MAINTAINERS
delete mode 100644 board/prodrive/alpr/Makefile
delete mode 100644 board/prodrive/alpr/alpr.c
delete mode 100644 board/prodrive/alpr/config.mk
delete mode 100644 board/prodrive/alpr/fpga.c
delete mode 100644 board/prodrive/alpr/init.S
delete mode 100644 board/prodrive/alpr/nand.c
delete mode 100644 configs/alpr_defconfig
delete mode 100644 include/configs/alpr.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 10b86e0..e8c0ca0 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -140,9 +140,6 @@ config TARGET_MIP405
config TARGET_PIP405
bool "Support PIP405"
-config TARGET_ALPR
- bool "Support alpr"
-
config TARGET_P3P440
bool "Support p3p440"
@@ -197,7 +194,6 @@ source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
source "board/pcs440ep/Kconfig"
-source "board/prodrive/alpr/Kconfig"
source "board/prodrive/p3p440/Kconfig"
source "board/sbc405/Kconfig"
source "board/t3corp/Kconfig"
diff --git a/board/prodrive/alpr/Kconfig b/board/prodrive/alpr/Kconfig
deleted file mode 100644
index 543b455..0000000
--- a/board/prodrive/alpr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ALPR
-
-config SYS_BOARD
- default "alpr"
-
-config SYS_VENDOR
- default "prodrive"
-
-config SYS_CONFIG_NAME
- default "alpr"
-
-endif
diff --git a/board/prodrive/alpr/MAINTAINERS b/board/prodrive/alpr/MAINTAINERS
deleted file mode 100644
index 31baabb..0000000
--- a/board/prodrive/alpr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ALPR BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/prodrive/alpr/
-F: include/configs/alpr.h
-F: configs/alpr_defconfig
diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
deleted file mode 100644
index 812d041..0000000
--- a/board/prodrive/alpr/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = alpr.o fpga.o nand.o
-extra-y += init.o
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
deleted file mode 100644
index 31c1ab5..0000000
--- a/board/prodrive/alpr/alpr.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <asm/ppc4xx-emac.h>
-#include <miiphy.h>
-#include <asm/processor.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int alpr_fpga_init(void);
-
-int board_early_init_f (void)
-{
- /*-------------------------------------------------------------------------
- * Initialize EBC CONFIG
- *-------------------------------------------------------------------------*/
- mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
- EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
- EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- /*
- * Because of the interrupt handling rework to handle 440GX interrupts
- * with the common code, we needed to change names of the UIC registers.
- * Here the new relationship:
- *
- * U-Boot name 440GX name
- * -----------------------
- * UIC0 UICB0
- * UIC1 UIC0
- * UIC2 UIC1
- * UIC3 UIC2
- */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
- mtdcr (UIC1ER, 0x00000000); /* disable all */
- mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (UIC1PR, 0xfffffe03); /* per manual */
- mtdcr (UIC1TR, 0x01c00000); /* per manual */
- mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
- mtdcr (UIC2ER, 0x00000000); /* disable all */
- mtdcr (UIC2CR, 0x00000000); /* all non-critical */
- mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
- mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
- mtdcr (UIC3ER, 0x00000000); /* disable all */
- mtdcr (UIC3CR, 0x00000000); /* all non-critical */
- mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC0SR, 0xfc000000); /* clear all */
- mtdcr (UIC0ER, 0x00000000); /* disable all */
- mtdcr (UIC0CR, 0x00000000); /* all non-critical */
- mtdcr (UIC0PR, 0xfc000000); /* */
- mtdcr (UIC0TR, 0x00000000); /* */
- mtdcr (UIC0VR, 0x00000001); /* */
-
- /* Setup shutdown/SSD empty interrupt as inputs */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
-
- /* Setup GPIO/IRQ multiplexing */
- mtsdr(SDR0_PFC0, 0x01a33e00);
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- unsigned short reg;
-
- /*
- * Configure LED's of both Marvell 88E1111 PHY's
- *
- * This has to be done after the 4xx ethernet driver is loaded,
- * so "last_stage_init()" is the right place.
- */
- miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
- reg |= 0x0001;
- miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
- miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
- reg |= 0x0001;
- miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
-
- return 0;
-}
-
-static int board_rev(void)
-{
- /* Setup as input */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
-
- return (in32(GPIO0_IR) >> 16) & 0x3;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf ("Board: ALPR");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- printf(" (Rev. %d)\n", board_rev());
-
- return (0);
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Override weak pci_pre_init()
- */
-int pci_pre_init(struct pci_controller *hose)
-{
- if (__pci_pre_init(hose) == 0)
- return 0;
-
- /* FPGA Init */
- alpr_fpga_init();
-
- return 1;
-}
-
-/*************************************************************************
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-static void wait_for_pci_ready(void)
-{
- /*
- * Configure EREADY as input
- */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
- udelay(1000);
-
- for (;;) {
- if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
- return;
- }
-
-}
-
-int is_pci_host(struct pci_controller *hose)
-{
- wait_for_pci_ready();
- return 1; /* return 1 for host controller */
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- | PowerPC440 PCI Master configuration.
- | Map PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r( PCIL0_POM0SA, 0 ); /* disable */
- out32r( PCIL0_POM1SA, 0 ); /* disable */
- out32r( PCIL0_POM2SA, 0 ); /* disable */
-
- out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
-
- out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk
deleted file mode 100644
index 0ccb2e6..0000000
--- a/board/prodrive/alpr/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
deleted file mode 100644
index 3133f94..0000000
--- a/board/prodrive/alpr/fpga.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs at denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Altera FPGA configuration support for the ALPR computer from prodrive
- */
-
-#include <common.h>
-#include <altera.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt, args...) printf(fmt , ##args)
-#else
-#define PRINTF(fmt, args...)
-#endif
-
-static unsigned long regval;
-
-#define SET_GPIO_REG_0(reg, bit) do { \
- regval = in32(reg); \
- regval &= ~(0x80000000 >> bit); \
- out32(reg, regval); \
- } while (0)
-
-#define SET_GPIO_REG_1(reg, bit) do { \
- regval = in32(reg); \
- regval |= (0x80000000 >> bit); \
- out32(reg, regval); \
- } while (0)
-
-#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
-#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
-
-#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
-#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
-#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
-#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
-#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
-
-#define SET_FPGA(data) out32(GPIO0_OR, data)
-
-#define FPGA_WRITE_1 do { \
- SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \
-} while (0)
-
-#define FPGA_WRITE_0 do { \
- SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \
- SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \
-} while (0)
-
-/* Plattforminitializations */
-/* Here we have to set the FPGA Chain */
-/* PROGRAM_PROG_EN = HIGH */
-/* PROGRAM_SEL_DPR = LOW */
-int fpga_pre_fn(int cookie)
-{
- /* Enable the FPGA Chain */
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
- SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
- SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
-
- /* initialize the GPIO Pins */
- /* output */
- SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
-
- /* output */
- SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
-
- /* First we set STATUS to 0 then as an input */
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
- SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
-
- /* output */
- SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
- SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
-
- /* input */
- SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
- SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
- SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
-
- /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
- SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
- return FPGA_SUCCESS;
-}
-
-/* Set the state of CONFIG Pin */
-int fpga_config_fn(int assert_config, int flush, int cookie)
-{
- if (assert_config)
- SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
- else
- SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
-
- return FPGA_SUCCESS;
-}
-
-/* Returns the state of STATUS Pin */
-int fpga_status_fn(int cookie)
-{
- unsigned long reg;
-
- reg = in32(GPIO0_IR);
- if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
- PRINTF("STATUS = HIGH\n");
- return FPGA_FAIL;
- }
- PRINTF("STATUS = LOW\n");
- return FPGA_SUCCESS;
-}
-
-/* Returns the state of CONF_DONE Pin */
-int fpga_done_fn(int cookie)
-{
- unsigned long reg;
- reg = in32(GPIO0_IR);
- if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
- PRINTF("CONF_DON = HIGH\n");
- return FPGA_FAIL;
- }
- PRINTF("CONF_DON = LOW\n");
- return FPGA_SUCCESS;
-}
-
-/* writes the complete buffer to the FPGA
- writing the complete buffer in one function is much faster,
- then calling it for every bit */
-int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
-{
- size_t bytecount = 0;
- unsigned char *data = (unsigned char *) buf;
- unsigned char val = 0;
- int i;
- int len_40 = len / 40;
-
- while (bytecount < len) {
- val = data[bytecount++];
- i = 8;
- do {
- if (val & 0x01)
- FPGA_WRITE_1;
- else
- FPGA_WRITE_0;
-
- val >>= 1;
- i--;
- } while (i > 0);
-
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (bytecount % len_40 == 0) {
- putc('.'); /* let them know we are alive */
-#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
- if (ctrlc())
- return FPGA_FAIL;
-#endif
- }
-#endif
- }
- return FPGA_SUCCESS;
-}
-
-/* called, when programming is aborted */
-int fpga_abort_fn(int cookie)
-{
- SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
- return FPGA_SUCCESS;
-}
-
-/* called, when programming was succesful */
-int fpga_post_fn(int cookie)
-{
- return fpga_abort_fn(cookie);
-}
-
-/* Note that these are pointers to code that is in Flash. They will be
- * relocated at runtime.
- */
-Altera_CYC2_Passive_Serial_fns fpga_fns = {
- fpga_pre_fn,
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_write_fn,
- fpga_abort_fn,
- fpga_post_fn
-};
-
-Altera_desc fpga[CONFIG_FPGA_COUNT] = {
- {Altera_CYC2,
- passive_serial,
- Altera_EP2C35_SIZE,
- (void *) &fpga_fns,
- NULL,
- 0}
-};
-
-/*
- * Initialize the fpga. Return 1 on success, 0 on failure.
- */
-int alpr_fpga_init(void)
-{
- int i;
-
- PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__);
- fpga_init();
-
- for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
- PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
- fpga_add(fpga_altera, &fpga[i]);
- }
- return 1;
-}
-
-#endif
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
deleted file mode 100644
index 7ff7a59..0000000
--- a/board/prodrive/alpr/init.S
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
- tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
-#ifdef CONFIG_4xx_DCACHE
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
-#else
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
-#endif
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
-
- /* PCI */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
-
- /* NAND */
- tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
- tlbtab_end
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
deleted file mode 100644
index ca40cea..0000000
--- a/board/prodrive/alpr/nand.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs at denx.de
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <asm/processor.h>
-#include <nand.h>
-
-struct alpr_ndfc_regs {
- u8 cmd[4];
- u8 addr_wait;
- u8 term;
- u8 dummy;
- u8 dummy2;
- u8 data;
-};
-
-static u8 hwctl;
-static struct alpr_ndfc_regs *alpr_ndfc = NULL;
-
-#define readb(addr) (u8)(*(volatile u8 *)(addr))
-#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
-
-/*
- * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
- * the NAND devices. The NDFC has command, address and data registers that
- * when accessed will set up the NAND flash pins appropriately. We'll use the
- * hwcontrol function to save the configuration in a global variable.
- * We can then use this information in the read and write functions to
- * determine which NDFC register to access.
- *
- * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
- */
-static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- hwctl |= 0x1;
- else
- hwctl &= ~0x1;
- if ( ctrl & NAND_ALE )
- hwctl |= 0x2;
- else
- hwctl &= ~0x2;
- if ( (ctrl & NAND_NCE) != NAND_NCE)
- writeb(0x00, &(alpr_ndfc->term));
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static u_char alpr_nand_read_byte(struct mtd_info *mtd)
-{
- return readb(&(alpr_ndfc->data));
-}
-
-static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *nand = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- if (hwctl & 0x1)
- /*
- * IO_ADDR_W used as CMD[i] reg to support multiple NAND
- * chips.
- */
- writeb(buf[i], nand->IO_ADDR_W);
- else if (hwctl & 0x2)
- writeb(buf[i], &(alpr_ndfc->addr_wait));
- else
- writeb(buf[i], &(alpr_ndfc->data));
- }
-}
-
-static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- buf[i] = readb(&(alpr_ndfc->data));
- }
-}
-
-static int alpr_nand_dev_ready(struct mtd_info *mtd)
-{
- /*
- * Blocking read to wait for NAND to be ready
- */
- (void)readb(&(alpr_ndfc->addr_wait));
-
- /*
- * Return always true
- */
- return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
-
- nand->ecc.mode = NAND_ECC_SOFT;
-
- /* Reference hardware control function */
- nand->cmd_ctrl = alpr_nand_hwcontrol;
- nand->read_byte = alpr_nand_read_byte;
- nand->write_buf = alpr_nand_write_buf;
- nand->read_buf = alpr_nand_read_buf;
- nand->dev_ready = alpr_nand_dev_ready;
-
- return 0;
-}
-#endif
diff --git a/configs/alpr_defconfig b/configs/alpr_defconfig
deleted file mode 100644
index b7cd74d..0000000
--- a/configs/alpr_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ALPR=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index fb1ed42..cdb2b6e 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,7 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-cam_enc_4xx arm arm926ejs - - Heiko Schocher <hs@denx.de>
+alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
+cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
deleted file mode 100644
index f113ebd..0000000
--- a/include/configs/alpr.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_ALPR 1 /* Board is ebony */
-#define CONFIG_440GX 1 /* Specifc GX support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
-#undef CONFIG_SDRAM_ECC /* enable ECC support */
-#define CONFIG_SYS_SDRAM_TABLE { \
- {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
- {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (PCF8594C)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
- /* 8 byte page write mode using */
- /* last 3 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run kernelx\" to boot the system;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth3\0" \
- "hostname=alpr\0" \
- "fdt_file=alpr/alpr.dtb\0" \
- "fdt_addr=400000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} ${init}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
- "mem=193M\0" \
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "net_nfs_fdt=tftp 200000 ${bootfile};" \
- "tftp ${fdt_addr} ${fdt_file};" \
- "run nfsargs addip addtty;" \
- "bootm 200000 - ${fdt_addr}\0" \
- "rootpath=/opt/projects/alpr/nfs_root\0" \
- "bootfile=/alpr/uImage\0" \
- "kernel_addr=fff00000\0" \
- "ramdisk_addr=fff10000\0" \
- "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "ethprime=ppc_4xx_eth3\0" \
- "ethact=ppc_4xx_eth3\0" \
- "autoload=no\0" \
- "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
- "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
- "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
- "rootfstype=jffs2 init=/sbin/init\0" \
- "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
- ";bootm 200000\0" \
- "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
- "addtty;bootm 200000\0" \
- "kernel1=setenv actkernel 'kernel1';run load_fpga " \
- "kernel1_mtd\0" \
- "kernel2=setenv actkernel 'kernel2';run load_fpga " \
- "kernel2_mtd\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run kernel2"
-
-#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
-#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
-#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
-#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- *-----------------------------------------------------------------------*/
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
- Reihe geschaltet -> sollte gehen,
- aufpassen mit Datasize ist jetzt
- halt doppelt so gross ... Seite 306
- ist das mit den multiple Device in PS
- Mode erklaert ...*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
-#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
-#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
-#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
-#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
-
-#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
-#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
-#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup
- *-----------------------------------------------------------------------*/
-#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
-#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
-#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
-#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
-#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
- CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
-#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 2/9] powerpc: ppc4xx: remove csb272, csb472 support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
2015-09-02 1:40 ` [U-Boot] [PATCH v2 1/9] powerpc: ppc4xx: remove alpr support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:58 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 3/9] powerpc: ppc4xx: remove lwmon5 support Masahiro Yamada
` (6 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tolunay Orkun <torkun@nextio.com>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 8 --
board/csb272/Kconfig | 9 --
board/csb272/MAINTAINERS | 6 -
board/csb272/Makefile | 9 --
board/csb272/csb272.c | 171 ------------------------
board/csb272/init.S | 196 ----------------------------
board/csb472/Kconfig | 9 --
board/csb472/MAINTAINERS | 6 -
board/csb472/Makefile | 9 --
board/csb472/csb472.c | 138 --------------------
board/csb472/init.S | 192 ---------------------------
configs/csb272_defconfig | 4 -
configs/csb472_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/csb272.h | 282 ----------------------------------------
include/configs/csb472.h | 281 ---------------------------------------
16 files changed, 1 insertion(+), 1324 deletions(-)
delete mode 100644 board/csb272/Kconfig
delete mode 100644 board/csb272/MAINTAINERS
delete mode 100644 board/csb272/Makefile
delete mode 100644 board/csb272/csb272.c
delete mode 100644 board/csb272/init.S
delete mode 100644 board/csb472/Kconfig
delete mode 100644 board/csb472/MAINTAINERS
delete mode 100644 board/csb472/Makefile
delete mode 100644 board/csb472/csb472.c
delete mode 100644 board/csb472/init.S
delete mode 100644 configs/csb272_defconfig
delete mode 100644 configs/csb472_defconfig
delete mode 100644 include/configs/csb272.h
delete mode 100644 include/configs/csb472.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index e8c0ca0..c6bbe12 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,12 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_CSB272
- bool "Support csb272"
-
-config TARGET_CSB472
- bool "Support csb472"
-
config TARGET_LWMON5
bool "Support lwmon5"
select SUPPORT_SPL
@@ -176,8 +170,6 @@ source "board/amcc/yosemite/Kconfig"
source "board/amcc/yucca/Kconfig"
source "board/avnet/fx12mm/Kconfig"
source "board/avnet/v5fx30teval/Kconfig"
-source "board/csb272/Kconfig"
-source "board/csb472/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
diff --git a/board/csb272/Kconfig b/board/csb272/Kconfig
deleted file mode 100644
index eed04f0..0000000
--- a/board/csb272/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CSB272
-
-config SYS_BOARD
- default "csb272"
-
-config SYS_CONFIG_NAME
- default "csb272"
-
-endif
diff --git a/board/csb272/MAINTAINERS b/board/csb272/MAINTAINERS
deleted file mode 100644
index 4bc95ea..0000000
--- a/board/csb272/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CSB272 BOARD
-M: Tolunay Orkun <torkun@nextio.com>
-S: Maintained
-F: board/csb272/
-F: include/configs/csb272.h
-F: configs/csb272_defconfig
diff --git a/board/csb272/Makefile b/board/csb272/Makefile
deleted file mode 100644
index 36ec9b6..0000000
--- a/board/csb272/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = csb272.o
-obj-y += init.o
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
deleted file mode 100644
index dc2c950..0000000
--- a/board/csb272/csb272.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun at nextio.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/ppc4xx-emac.h>
-
-void sdram_init(void);
-
-/*
- * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
- *
- * CLKA output => Epson LCD Controller
- * CLKB output => Not Connected
- * CLKC output => Ethernet
- * CLKD output => UART external clock
- *
- * Note: these values are obtained from device after init by micromonitor
-*/
-uchar pll_fs6377_regs[16] = {
- 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
- 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
-
-/*
- * pll_init: Initialize AMIS IC FS6377-01 PLL
- *
- * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
- *
- */
-int pll_init(void)
-{
- i2c_set_bus_num(0);
-
- return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
- (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
-}
-
-/*
- * board_early_init_f: do early board initialization
- *
- */
-int board_early_init_f(void)
-{
- /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
- (void) get_clocks();
- pll_init();
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
-
- return 0; /* success */
-}
-
-/*
- * checkboard: identify/verify the board we are running
- *
- * Remark: we just assume it is correct board here!
- *
- */
-int checkboard(void)
-{
- printf("BOARD: Cogent CSB272\n");
-
- return 0; /* success */
-}
-
-/*
- * initram: Determine the size of mounted DRAM
- *
- * Size is determined by reading SDRAM configuration registers as
- * configured by initialization code
- *
- */
-phys_size_t initdram (int board_type)
-{
- ulong tot_size;
- ulong bank_size;
- ulong tmp;
-
- /*
- * ToDo: Move the asm init routine sdram_init() to this C file,
- * or even better use some common ppc4xx code available
- * in arch/powerpc/cpu/ppc4xx
- */
- sdram_init();
-
- tot_size = 0;
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- return tot_size;
-}
-
-/*
- * last_stage_init: final configurations (such as PHY etc)
- *
- */
-int last_stage_init(void)
-{
- /* initialize the PHY */
- miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-
- /* AUTO neg */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-
- /* LEDs */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
-
-
- return 0; /* success */
-}
diff --git a/board/csb272/init.S b/board/csb272/init.S
deleted file mode 100644
index bf1d986..0000000
--- a/board/csb272/init.S
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define LI32(reg,val) \
- addis reg,0,val at h;\
- ori reg,reg,val at l
-
-#define WDCR_EBC(reg,val) \
- addi r4,0,reg;\
- mtdcr EBC0_CFGADDR,r4;\
- addis r4,0,val at h;\
- ori r4,r4,val at l;\
- mtdcr EBC0_CFGDATA,r4
-
-#define WDCR_SDRAM(reg,val) \
- addi r4,0,reg;\
- mtdcr SDRAM0_CFGADDR,r4;\
- addis r4,0,val at h;\
- ori r4,r4,val at l;\
- mtdcr SDRAM0_CFGDATA,r4
-
-/******************************************************************************
- * Function: ext_bus_cntlr_init
- *
- * Description: Configures EBC Controller and a few basic chip selects.
- *
- * CS0 is setup to get the Boot Flash out of the addresss range
- * so that we may setup a stack. CS7 is setup so that we can
- * access and reset the hardware watchdog.
- *
- * IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl ext_bus_cntlr_init
- .type ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
- mflr r0
- /********************************************************************
- * Prefetch entire ext_bus_cntrl_init function into the icache.
- * This is necessary because we are going to change the same CS we
- * are executing from. Otherwise a CPU lockup may occur.
- *******************************************************************/
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
-
- /* Calculate number of cache lines for this function */
- addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
- mtctr r4
-..ebcloop:
- icbt r0, r3 /* prefetch cache line for addr in r3*/
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
- bdnz ..ebcloop /* continue for $CTR cache lines */
-
- /********************************************************************
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings. 200usec should be enough.
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
- *******************************************************************/
- addis r3, 0, 0x0
- ori r3, r3, 0xA000 /* wait 200us from reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /********************************************************************
- * SETUP CPC0_CR0
- *******************************************************************/
- LI32(r4, 0x007000c0)
- mtdcr CPC0_CR0, r4
-
- /********************************************************************
- * Setup CPC0_CR1: Change PCIINT signal to PerWE
- *******************************************************************/
- mfdcr r4, CPC0_CR1
- ori r4, r4, 0x4000
- mtdcr CPC0_CR1, r4
-
- /********************************************************************
- * Setup External Bus Controller (EBC).
- *******************************************************************/
- WDCR_EBC(EBC0_CFG, 0xd84c0000)
- /********************************************************************
- * Memory Bank 0 (Intel 28F128J3 Flash) initialization
- *******************************************************************/
- /*WDCR_EBC(PB1AP, 0x02869200)*/
- WDCR_EBC(PB1AP, 0x07869200)
- WDCR_EBC(PB0CR, 0xfe0bc000)
- /********************************************************************
- * Memory Bank 1 (Holtek HT6542B PS/2) initialization
- *******************************************************************/
- WDCR_EBC(PB1AP, 0x1f869200)
- WDCR_EBC(PB1CR, 0xf0818000)
- /********************************************************************
- * Memory Bank 2 (Epson S1D13506) initialization
- *******************************************************************/
- WDCR_EBC(PB2AP, 0x05860300)
- WDCR_EBC(PB2CR, 0xf045a000)
- /********************************************************************
- * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
- *******************************************************************/
- WDCR_EBC(PB3AP, 0x0387d200)
- WDCR_EBC(PB3CR, 0xf021c000)
- /********************************************************************
- * Memory Bank 4-7 (Unused) initialization
- *******************************************************************/
- WDCR_EBC(PB4AP, 0)
- WDCR_EBC(PB4CR, 0)
- WDCR_EBC(PB5AP, 0)
- WDCR_EBC(PB5CR, 0)
- WDCR_EBC(PB6AP, 0)
- WDCR_EBC(PB6CR, 0)
- WDCR_EBC(PB7AP, 0)
- WDCR_EBC(PB7CR, 0)
-
- /* We are all done */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function: sdram_init
- *
- * Description: Configures SDRAM memory banks.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl sdram_init
- .type sdram_init, @function
-sdram_init:
-
- /*
- * Disable memory controller to allow
- * values to be changed.
- */
- WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
-
- /*
- * Configure Memory Banks
- */
- WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
- WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
- WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
- WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
-
- /*
- * Set up SDTR1 (SDRAM Timing Register)
- */
- WDCR_SDRAM(SDRAM0_TR, 0x00854009)
-
- /*
- * Set RTR (Refresh Timing Register)
- */
- WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
- /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
-
- /********************************************************************
- * Delay to ensure 200usec have elapsed since reset. Assume worst
- * case that the core is running 200Mhz:
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- *******************************************************************/
- addis r3, 0, 0x0000
- ori r3, r3, 0xA000 /* Wait >200us from reset */
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 /* spin loop */
-
- /********************************************************************
- * Set memory controller options reg, MCOPT1.
- *******************************************************************/
- WDCR_SDRAM(SDRAM0_CFG,0x80800000)
-
-..sdri_done:
- blr /* Return to calling function */
-.Lfe1: .size sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */
diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig
deleted file mode 100644
index 53b1e7a..0000000
--- a/board/csb472/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CSB472
-
-config SYS_BOARD
- default "csb472"
-
-config SYS_CONFIG_NAME
- default "csb472"
-
-endif
diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS
deleted file mode 100644
index 25041ed..0000000
--- a/board/csb472/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CSB472 BOARD
-M: Tolunay Orkun <torkun@nextio.com>
-S: Maintained
-F: board/csb472/
-F: include/configs/csb472.h
-F: configs/csb472_defconfig
diff --git a/board/csb472/Makefile b/board/csb472/Makefile
deleted file mode 100644
index 5f7e8b5..0000000
--- a/board/csb472/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = csb472.o
-obj-y += init.o
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
deleted file mode 100644
index b1de18c..0000000
--- a/board/csb472/csb472.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun at nextio.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/ppc4xx-emac.h>
-
-void sdram_init(void);
-
-/*
- * board_early_init_f: do early board initialization
- *
- */
-int board_early_init_f(void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
-
- return 0; /* success */
-}
-
-/*
- * checkboard: identify/verify the board we are running
- *
- * Remark: we just assume it is correct board here!
- *
- */
-int checkboard(void)
-{
- printf("BOARD: Cogent CSB472\n");
-
- return 0; /* success */
-}
-
-/*
- * initram: Determine the size of mounted DRAM
- *
- * Size is determined by reading SDRAM configuration registers as
- * configured by initialization code
- *
- */
-phys_size_t initdram (int board_type)
-{
- ulong tot_size;
- ulong bank_size;
- ulong tmp;
-
- /*
- * ToDo: Move the asm init routine sdram_init() to this C file,
- * or even better use some common ppc4xx code available
- * in arch/powerpc/cpu/ppc4xx
- */
- sdram_init();
-
- tot_size = 0;
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- tmp = mfdcr (SDRAM0_CFGDATA);
- if (tmp & 0x00000001) {
- bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
- tot_size += bank_size;
- }
-
- return tot_size;
-}
-
-/*
- * last_stage_init: final configurations (such as PHY etc)
- *
- */
-int last_stage_init(void)
-{
- /* initialize the PHY */
- miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-
- /* AUTO neg */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-
- /* LEDs */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
-
- return 0; /* success */
-}
diff --git a/board/csb472/init.S b/board/csb472/init.S
deleted file mode 100644
index 7383a70..0000000
--- a/board/csb472/init.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define LI32(reg,val) \
- addis reg,0,val at h;\
- ori reg,reg,val at l
-
-#define WDCR_EBC(reg,val) \
- addi r4,0,reg;\
- mtdcr EBC0_CFGADDR,r4;\
- addis r4,0,val at h;\
- ori r4,r4,val at l;\
- mtdcr EBC0_CFGDATA,r4
-
-#define WDCR_SDRAM(reg,val) \
- addi r4,0,reg;\
- mtdcr SDRAM0_CFGADDR,r4;\
- addis r4,0,val at h;\
- ori r4,r4,val at l;\
- mtdcr SDRAM0_CFGDATA,r4
-
-/******************************************************************************
- * Function: ext_bus_cntlr_init
- *
- * Description: Configures EBC Controller and a few basic chip selects.
- *
- * CS0 is setup to get the Boot Flash out of the addresss range
- * so that we may setup a stack. CS7 is setup so that we can
- * access and reset the hardware watchdog.
- *
- * IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl ext_bus_cntlr_init
- .type ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
- mflr r0
- /********************************************************************
- * Prefetch entire ext_bus_cntrl_init function into the icache.
- * This is necessary because we are going to change the same CS we
- * are executing from. Otherwise a CPU lockup may occur.
- *******************************************************************/
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
-
- /* Calculate number of cache lines for this function */
- addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
- mtctr r4
-..ebcloop:
- icbt r0, r3 /* prefetch cache line for addr in r3*/
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
- bdnz ..ebcloop /* continue for $CTR cache lines */
-
- /********************************************************************
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings. 200usec should be enough.
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
- *******************************************************************/
- addis r3, 0, 0x0
- ori r3, r3, 0xA000 /* wait 200us from reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /********************************************************************
- * SETUP CPC0_CR0
- *******************************************************************/
- LI32(r4, 0x00c01030)
- mtdcr CPC0_CR0, r4
-
- /********************************************************************
- * Setup CPC0_CR1: Change PCIINT signal to PerWE
- *******************************************************************/
- mfdcr r4, CPC0_CR1
- ori r4, r4, 0x4000
- mtdcr CPC0_CR1, r4
-
- /********************************************************************
- * Setup External Bus Controller (EBC).
- *******************************************************************/
- WDCR_EBC(EBC0_CFG, 0xd84c0000)
- /********************************************************************
- * Memory Bank 0 (Intel 28F640J3 Flash) initialization
- *******************************************************************/
- /*WDCR_EBC(PB1AP, 0x03055200)*/
- /*WDCR_EBC(PB1AP, 0x04055200)*/
- WDCR_EBC(PB1AP, 0x08055200)
- WDCR_EBC(PB0CR, 0xff87a000)
- /********************************************************************
- * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
- *******************************************************************/
- /*WDCR_EBC(PB3AP, 0x07869200)*/
- WDCR_EBC(PB3AP, 0x04055200)
- WDCR_EBC(PB3CR, 0xf081c000)
- /********************************************************************
- * Memory Bank 1,2,4-7 (Unused) initialization
- *******************************************************************/
- WDCR_EBC(PB1AP, 0)
- WDCR_EBC(PB1CR, 0)
- WDCR_EBC(PB2AP, 0)
- WDCR_EBC(PB2CR, 0)
- WDCR_EBC(PB4AP, 0)
- WDCR_EBC(PB4CR, 0)
- WDCR_EBC(PB5AP, 0)
- WDCR_EBC(PB5CR, 0)
- WDCR_EBC(PB6AP, 0)
- WDCR_EBC(PB6CR, 0)
- WDCR_EBC(PB7AP, 0)
- WDCR_EBC(PB7CR, 0)
-
- /* We are all done */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function: sdram_init
- *
- * Description: Configures SDRAM memory banks.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl sdram_init
- .type sdram_init, @function
-sdram_init:
-
- /*
- * Disable memory controller to allow
- * values to be changed.
- */
- WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
-
- /*
- * Configure Memory Banks
- */
- WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
- WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
- WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
- WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
-
- /*
- * Set up SDTR1 (SDRAM Timing Register)
- */
- WDCR_SDRAM(SDRAM0_TR, 0x00854009)
-
- /*
- * Set RTR (Refresh Timing Register)
- */
- WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
- /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
-
- /********************************************************************
- * Delay to ensure 200usec have elapsed since reset. Assume worst
- * case that the core is running 200Mhz:
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- *******************************************************************/
- addis r3, 0, 0x0000
- ori r3, r3, 0xA000 /* Wait >200us from reset */
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 /* spin loop */
-
- /********************************************************************
- * Set memory controller options reg, MCOPT1.
- *******************************************************************/
- WDCR_SDRAM(SDRAM0_CFG,0x80800000)
-
-..sdri_done:
- blr /* Return to calling function */
-.Lfe1: .size sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */
diff --git a/configs/csb272_defconfig b/configs/csb272_defconfig
deleted file mode 100644
index c9cc680..0000000
--- a/configs/csb272_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CSB272=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/csb472_defconfig b/configs/csb472_defconfig
deleted file mode 100644
index e46b965..0000000
--- a/configs/csb472_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CSB472=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index cdb2b6e..87e2b35 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>
alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
deleted file mode 100644
index 71cb5df..0000000
--- a/include/configs/csb272.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun at nextio.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
-#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * OS Bootstrap configuration
- *
- */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
-
-#if 1
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/ram rw ramdisk_size=4096 " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm fe000000 fe100000"
-#endif
-
-#if 0
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-
-/*
- * Serial download configuration
- *
- */
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * KGDB Configuration
- *
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- *
- */
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * watchdog configuration
- *
- */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * UART configuration
- *
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
-#undef CONFIG_SYS_BASE_BAUD
-#define CONFIG_BAUDRATE 38400 /* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * I2C configuration
- *
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
-
-/*
- * MII PHY configuration
- *
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
- /* 32usec min. for LXT971A */
-#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
-
-/*
- * RTC configuration
- *
- * Note that DS1307 RTC is limited to 100Khz I2C bus.
- *
- */
-#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
-
-/*
- * PCI stuff
- *
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*
- * IDE stuff
- *
- */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-/*
- * Environment configuration
- *
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-
-/*
- * General Memory organization
- *
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
-#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
-#endif
-
-/*
- * FLASH Device configuration
- *
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/*
- * On Chip Memory location/size
- *
- */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*
- * Global info and initial stack
- *
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Miscellaneous board specific definitions
- *
- */
-#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
-#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
deleted file mode 100644
index 5bd3867..0000000
--- a/include/configs/csb472.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun at nextio.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
-#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-/*
- * OS Bootstrap configuration
- *
- */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
-
-#if 1
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/ram rw ramdisk_size=4096 " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm ff800000 ff900000"
-#endif
-
-#if 0
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/*
- * Serial download configuration
- *
- */
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * KGDB Configuration
- *
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- *
- */
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * watchdog configuration
- *
- */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * UART configuration
- *
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 38400 /* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * I2C configuration
- *
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
-
-/*
- * MII PHY configuration
- *
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
- /* 32usec min. for LXT971A */
-#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
-
-/*
- * RTC configuration
- *
- * Note that DS1307 RTC is limited to 100Khz I2C bus.
- *
- */
-#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
-
-/*
- * PCI stuff
- *
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*
- * IDE stuff
- *
- */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-/*
- * Environment configuration
- *
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-
-/*
- * General Memory organization
- *
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start@0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
-#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
-#endif
-
-/*
- * FLASH Device configuration
- *
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/*
- * On Chip Memory location/size
- *
- */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*
- * Global info and initial stack
- *
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Miscellaneous board specific definitions
- *
- */
-#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [U-Boot, v2, 2/9] powerpc: ppc4xx: remove csb272, csb472 support
2015-09-02 1:40 ` [U-Boot] [PATCH v2 2/9] powerpc: ppc4xx: remove csb272, csb472 support Masahiro Yamada
@ 2015-09-02 21:58 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-09-02 21:58 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 10:40:23AM +0900, Masahiro Yamada wrote:
> These have not been converted to Generic Board, so should be removed.
> (See doc/README.generic-board for details.)
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Tolunay Orkun <torkun@nextio.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 3/9] powerpc: ppc4xx: remove lwmon5 support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
2015-09-02 1:40 ` [U-Boot] [PATCH v2 1/9] powerpc: ppc4xx: remove alpr support Masahiro Yamada
2015-09-02 1:40 ` [U-Boot] [PATCH v2 2/9] powerpc: ppc4xx: remove csb272, csb472 support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 4/9] powerpc: ppc4xx: remove p3p440 support Masahiro Yamada
` (5 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Remove CONFIG_LWMON5 references.
(Also, remove undefined CONFIG_WD_MAX_RATE while I am here.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 5 -
arch/powerpc/include/asm/global_data.h | 6 -
board/lwmon5/Kconfig | 9 -
board/lwmon5/MAINTAINERS | 7 -
board/lwmon5/Makefile | 9 -
board/lwmon5/config.mk | 18 -
board/lwmon5/init.S | 75 ----
board/lwmon5/kbd.c | 490 -----------------------
board/lwmon5/lwmon5.c | 558 --------------------------
board/lwmon5/sdram.c | 247 ------------
configs/lcd4_lwmon5_defconfig | 6 -
configs/lwmon5_defconfig | 4 -
doc/README.scrapyard | 1 +
drivers/video/mb862xx.c | 3 +-
include/configs/lwmon5.h | 692 ---------------------------------
15 files changed, 2 insertions(+), 2128 deletions(-)
delete mode 100644 board/lwmon5/Kconfig
delete mode 100644 board/lwmon5/MAINTAINERS
delete mode 100644 board/lwmon5/Makefile
delete mode 100644 board/lwmon5/config.mk
delete mode 100644 board/lwmon5/init.S
delete mode 100644 board/lwmon5/kbd.c
delete mode 100644 board/lwmon5/lwmon5.c
delete mode 100644 board/lwmon5/sdram.c
delete mode 100644 configs/lcd4_lwmon5_defconfig
delete mode 100644 configs/lwmon5_defconfig
delete mode 100644 include/configs/lwmon5.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index c6bbe12..883463a 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,10 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_LWMON5
- bool "Support lwmon5"
- select SUPPORT_SPL
-
config TARGET_PCS440EP
bool "Support pcs440ep"
@@ -181,7 +177,6 @@ source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 4090975..2527ef8 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -106,12 +106,6 @@ struct arch_global_data {
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
-#if defined(CONFIG_WD_MAX_RATE)
- unsigned long long wdt_last; /* trace watch-dog triggering rate */
-#endif
-#if defined(CONFIG_LWMON5)
- unsigned long kbd_status;
-#endif
};
#include <asm-generic/global_data.h>
diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig
deleted file mode 100644
index 90566d8..0000000
--- a/board/lwmon5/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_LWMON5
-
-config SYS_BOARD
- default "lwmon5"
-
-config SYS_CONFIG_NAME
- default "lwmon5"
-
-endif
diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS
deleted file mode 100644
index 7402ab6..0000000
--- a/board/lwmon5/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-LWMON5 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/lwmon5/
-F: include/configs/lwmon5.h
-F: configs/lcd4_lwmon5_defconfig
-F: configs/lwmon5_defconfig
diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile
deleted file mode 100644
index 02478ca..0000000
--- a/board/lwmon5/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lwmon5.o kbd.o sdram.o
-extra-y += init.o
diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
deleted file mode 100644
index d0348e8..0000000
--- a/board/lwmon5/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
deleted file mode 100644
index e5207c2..0000000
--- a/board/lwmon5/init.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
- /* TLB-entry for the FPGA Chip select 2 */
- tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the FPGA Chip select 3 */
- tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the LIME Controller */
- tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
-
- /*TLB-entry PCI registers*/
- tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry for peripherals */
- tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- tlbtab_end
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
deleted file mode 100644
index 97962da..0000000
--- a/board/lwmon5/kbd.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd at denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h> /* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG 0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG 0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define KEYBD_CMD_READ_KEYS 0x01
-#define KEYBD_CMD_READ_VERSION 0x02
-#define KEYBD_CMD_READ_STATUS 0x03
-#define KEYBD_CMD_RESET_ERRORS 0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK 0x3F
-#define KEYBD_STATUS_H_RESET 0x20
-#define KEYBD_STATUS_BROWNOUT 0x10
-#define KEYBD_STATUS_WD_RESET 0x08
-#define KEYBD_STATUS_OVERLOAD 0x04
-#define KEYBD_STATUS_ILLEGAL_WR 0x02
-#define KEYBD_STATUS_ILLEGAL_RD 0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN 2 /* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define KEYBD_DATALEN 6 /* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function: int board_postclk_init (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: This function is the board_postclk_init() method implementation
-Z* for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
- kbd_init();
-
- return (0);
-}
-
-static void kbd_init (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar tmp_data[KEYBD_DATALEN];
- uchar val, errcd;
- int i;
-
- i2c_set_bus_num(0);
-
- gd->arch.kbd_status = 0;
-
- /* Forced by PIC. Delays <= 175us loose */
- udelay(1000);
-
- /* Read initial keyboard error code */
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &errcd, 1);
- /* clear unused bits */
- errcd &= KEYBD_STATUS_MASK;
- /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
- errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
- if (errcd) {
- gd->arch.kbd_status |= errcd << 8;
- }
- /* Reset error code and verify */
- val = KEYBD_CMD_RESET_ERRORS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- udelay(1000); /* delay NEEDED by keyboard PIC !!! */
-
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &val, 1);
-
- val &= KEYBD_STATUS_MASK; /* clear unused bits */
- if (val) { /* permanent error, report it */
- gd->arch.kbd_status |= val;
- return;
- }
-
- /*
- * Read current keyboard state.
- *
- * After the error reset it may take some time before the
- * keyboard PIC picks up a valid keyboard scan - the total
- * scan time is approx. 1.6 ms (information by Martin Rajek,
- * 28 Sep 2002). We read a couple of times for the keyboard
- * to stabilize, using a big enough delay.
- * 10 times should be enough. If the data is still changing,
- * we use what we get :-(
- */
-
- memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
- for (i=0; i<10; ++i) {
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
- /* consistent state, done */
- break;
- }
- /* remeber last state, delay, and retry */
- memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
- udelay (5000);
- }
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
- uchar buf[sizeof(*data)];
- int rval;
-
- if (i2c_read(dspic_addr, reg, 2, buf, 2))
- return -1;
-
- rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
- *data = (buf[0] << 8) | buf[1];
-
- return rval;
-}
-
-
-/***********************************************************************
-F* Function: int misc_init_r (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned, even in the case of a keyboard
-P* error.
- *
-Z* Intention: This function is the misc_init_r() method implementation
-Z* for the lwmon board.
-Z* The keyboard controller is initialized and the result
-Z* of a read copied to the environment variable "keybd".
-Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z* this key, and if found display to the LCD will be enabled.
-Z* The keys in "keybd" are checked against the magic
-Z* keycommands defined in the environment.
-Z* See also key_match().
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->arch.kbd_status >> 8;
- uchar kbd_status = gd->arch.kbd_status;
- uchar val;
- ushort data, inv_data;
- char *str;
- int i;
-
- if (kbd_init_status) {
- printf ("KEYBD: Error %02X\n", kbd_init_status);
- }
- if (kbd_status) { /* permanent error, report it */
- printf ("*** Keyboard error code %02X ***\n", kbd_status);
- sprintf (keybd_env, "%02X", kbd_status);
- setenv ("keybd", keybd_env);
- return 0;
- }
-
- /*
- * Now we know that we have a working keyboard, so disable
- * all output to the LCD except when a key press is detected.
- */
-
- if ((console_assign (stdout, "serial") < 0) ||
- (console_assign (stderr, "serial") < 0)) {
- printf ("Can't assign serial port as output device\n");
- }
-
- /* Read Version */
- val = KEYBD_CMD_READ_VERSION;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
- printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
- /* Read current keyboard state */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- /* read out start key from bse01 received via can */
- _dspic_read(DSPIC_PON_STATUS_REG, &data);
- /* check highbyte from status register */
- if (data > 0xFF) {
- _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
- /* check inverse data */
- if ((data+inv_data) == 0xFFFF) {
- /* don't overwrite local key */
- if (kbd_data[1] == 0) {
- /* read key value */
- _dspic_read(DSPIC_PON_KEY_REG, &data);
- str = (char *)&data;
- /* swap bytes */
- kbd_data[1] = str[1];
- kbd_data[2] = str[0];
- printf("CAN received startkey: 0x%X\n", data);
- }
- }
- }
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
-
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
- if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
- if ((console_assign (stdout, "lcd") < 0) ||
- (console_assign (stderr, "lcd") < 0)) {
- printf ("Can't assign LCD display as output device\n");
- }
- }
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
- return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- uchar compare[KEYBD_DATALEN-1];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-/***********************************************************************
-F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters: uchar *kbd_data
-P* - The keys to match against our magic definitions
-P*
-P* Returnvalue: uchar *
-P* - != NULL: Pointer to the corresponding command(s)
-P* NULL: No magic is about to happen
- *
-Z* Intention: Check if pressed key(s) match magic sequence,
-Z* and return the command string associated with that key(s).
-Z*
-Z* If no key press was decoded, NULL is returned.
-Z*
-Z* Note: the first character of the argument will be
-Z* overwritten with the "magic charcter code" of the
-Z* decoded key(s), or '\0'.
-Z*
-Z* Note: the string points to static environment data
-Z* and must be saved before you call any function that
-Z* modifies the environment.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
- debug ("### Check magic \"%s\"\n", magic);
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
- debug ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
- debug ("### Delete PREBOOT\n");
- *kbd_data = '\0';
- return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: Implement the "kbd" command.
-Z* The keyboard status is read. The result is printed on
-Z* the console and written into the "keybd" environment
-Z* variable.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar val;
- int i;
-
-#if 0 /* Done in kbd_init */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar val;
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
deleted file mode 100644
index e9aa0b7..0000000
--- a/board/lwmon5/lwmon5.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- /* PLB Write pipelining disabled. Denali Core workaround */
- mtdcr(PLB4A0_ACR, 0xDE000000);
- mtdcr(PLB4A1_ACR, 0xDE000000);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
- mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
- mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
- mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
- mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* Trace Pins are disabled. SDR0_PFC0 Register */
- mtsdr(SDR0_PFC0, 0x0);
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- /* SMII via ZMII */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_6;
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_6;
-
- /* enable SPI (SCP) */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- mtsdr(SDR0_PFC4, 0x80000000);
-
- /* PCI arbiter disabled */
- /* PCI Host Configuration disbaled */
- mfsdr(SDR0_PCI0, reg);
- reg = 0;
- mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
- gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
- /* enable the CAN transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
- reg = 0; /* reuse as counter */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
- & ~CONFIG_SYS_DSPIC_TEST_MASK);
- while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
- udelay(1000);
- }
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
- /* set "boot error" flag */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
- CONFIG_SYS_DSPIC_TEST_MASK);
- }
-#endif
-
- /*
- * Reset PHY's:
- * The PHY's need a 2nd reset pulse, since the MDIO address is latched
- * upon reset, and with the first reset upon powerup, the addresses are
- * not latched reliable, since the IRQ line is multiplexed with an
- * MDIO address. A 2nd reset@this time will make sure, that the
- * correct address is latched.
- */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
- return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
- return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
- return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
- u32 val0, val1;
-
- /*
- * lwmon5 is manufactured in 2 different board versions:
- * The lwmon5a board has 64MiB NOR flash instead of the
- * 128MiB of the original lwmon5. Unfortunately the CFI driver
- * will report 2 banks of 64MiB even for the smaller flash
- * chip, since the bank is mirrored. To fix this, we bring
- * one bank into CFI query mode and read its response. This
- * enables us to detect the real number of flash devices/
- * banks which will be used later on by the common CFI driver.
- */
-
- /* Put bank 0 into CFI command mode and read */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
- val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
- val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
- /* Reset flash again out of query mode */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
- /* When not identical, we have 2 different flash devices/banks */
- if (val0 != val1)
- return 0;
-
- /*
- * Now we're sure that we're running on a LWMON5a board with
- * only 64MiB NOR flash in one bank:
- *
- * Set flash base address and bank count for CFI driver probing.
- */
- cfi_flash_num_flash_banks = 1;
- lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 pbcr;
- int size_val = 0;
- u32 reg;
-#ifndef CONFIG_LCD4_LWMON5
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1, sdr0_srst;
-#endif
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mfebc(PB0CR, pbcr);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(PB0CR, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
- /* Env protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
-#ifndef CONFIG_LCD4_LWMON5
- /*
- * USB suff...
- */
-
- /* Reset USB */
- /* Reset of USB2PHY0 must be active at least 10 us */
- mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
- udelay(2000);
-
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
- SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
- SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
- udelay(2000);
-
- /* Errata CHIP_6 */
-
- /* 1. Set internal PHY configuration */
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* 2. De-assert internal PHY reset */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst);
-
- /* 3. Wait for more than 1 ms */
- udelay(2000);
-
- /* 4. De-assert USB 2.0 Host main reset */
- mfsdr(SDR0_SRST0, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst);
- udelay(1000);
-
- /* 5. De-assert reset of OPB2 cores */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
- mtsdr(SDR0_SRST1, sdr0_srst);
- udelay(1000);
-
- /* 6. Set EHCI Configure FLAG */
-
- /* 7. Reassert internal PHY reset: */
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
- udelay(1000);
-#endif
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
-#ifndef CONFIG_LCD4_LWMON5
- printf("USB: Host(int phy) Device(ext phy)\n");
-#endif
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
-#ifndef CONFIG_LCD4_LWMON5
- /*
- * Init matrix keyboard
- */
- misc_init_r_kbd();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-void hw_watchdog_reset(void)
-{
- int val;
-#if defined(CONFIG_WD_MAX_RATE)
- unsigned long long ct = get_ticks();
-
- /*
- * Don't allow watch-dog triggering more frequently than
- * the predefined value CONFIG_WD_MAX_RATE [ticks].
- */
- if (ct >= gd->arch.wdt_last) {
- if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
- return;
- } else {
- /* Time base counter had been reset */
- if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
- CONFIG_WD_MAX_RATE)
- return;
- }
- gd->arch.wdt_last = get_ticks();
-#endif
-
- /*
- * Toggle watchdog output
- */
- val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
- gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], "on") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
- else if ((strcmp(argv[1], "off") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
- else
- return cmd_usage(cmdtp);
-
- return 0;
-}
-
-U_BOOT_CMD(
- eepromwp, 2, 0, do_eeprom_wp,
- "eeprom write protect off/on",
- "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
- { 0x0100, 0x00000f00 },
- { 0x0020, 0x801401df },
- { 0x0024, 0x00000000 },
- { 0x0028, 0x00000000 },
- { 0x002c, 0x00000000 },
- { 0x0110, 0x00000000 },
- { 0x0114, 0x00000000 },
- { 0x0118, 0x01df0280 },
- { 0x0004, 0x031f0000 },
- { 0x0008, 0x027f027f },
- { 0x000c, 0x015f028f },
- { 0x0010, 0x020c0000 },
- { 0x0014, 0x01df01ea },
- { 0x0018, 0x00000000 },
- { 0x001c, 0x01e00280 },
- { 0x0100, 0x80010f00 },
- { 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
- return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- mb862xx.winSizeX = 640;
- mb862xx.winSizeY = 480;
- mb862xx.gdfBytesPP = 2;
- mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
- return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS 0x64
-
-static void board_backlight_brightness(int brightness)
-{
- if (brightness > 0) {
- /* pwm duty, lamp on */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
- } else {
- /* lamp off */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
- }
-}
-
-void board_backlight_switch(int flag)
-{
- char * param;
- int rc;
-
- if (flag) {
- param = getenv("brightness");
- rc = param ? simple_strtol(param, NULL, 10) : -1;
- if (rc < 0)
- rc = DEFAULT_BRIGHTNESS;
- } else {
- rc = 0;
- }
- board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
- if (line_number == 1)
- strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
- else
- info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
- gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
- char s[8];
-
- env_init();
- getenv_f("boot_os", s, sizeof(s));
- if ((s != NULL) && (strcmp(s, "yes") == 0))
- return 0;
-
- return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
- const gdc_regs *regs = board_get_regs();
-
- /*
- * Setup PFC registers, mainly for ethernet support
- * later on in Linux
- */
- board_early_init_f();
-
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
- udelay(300);
- out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
- while (regs->index) {
- out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
- regs->index, regs->value);
- regs++;
- }
-
- board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
deleted file mode 100644
index 5dfbb0b..0000000
--- a/board/lwmon5/sdram.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie at fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman at fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder at fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
- u32 val;
-
- mfsdram(DDR0_22, val);
- val &= DDR0_22_CTRL_RAW_MASK;
- if (val)
- return 1;
- else
- return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- if (is_ecc_enabled())
- puts(" (ECC");
- else
- puts(" (ECC not");
-
- get_sys_info(&board_cfg);
- printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
- mfsdram(DDR0_03, val);
- val = DDR0_03_CASLAT_DECODE(val);
- printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
- /*
- * Controller idle status cannot be determined for Denali
- * DDR2 code. Just return here.
- */
-}
-
-static void program_ecc(u32 start_address,
- u32 num_bytes,
- u32 tlb_word2_i_value)
-{
- u32 val;
- u32 current_addr = start_address;
- u32 size;
- int bytes_remaining;
-
- sync();
- wait_ddr_idle();
-
- /*
- * Because of 440EPx errata CHIP 11, we don't touch the last 256
- * bytes of SDRAM.
- */
- bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
- /*
- * We have to write the ECC bytes by zeroing and flushing in smaller
- * steps, since the whole 256MByte takes too long for the external
- * watchdog.
- */
- while (bytes_remaining > 0) {
- size = min((64 << 20), bytes_remaining);
-
- /* Write zero's to SDRAM */
- dcbz_area(current_addr, size);
-
- /* Write modified dcache lines back to memory */
- clean_dcache_range(current_addr, current_addr + size);
-
- current_addr += 64 << 20;
- bytes_remaining -= 64 << 20;
- WATCHDOG_RESET();
- }
-
- sync();
- wait_ddr_idle();
-
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
- sync();
- wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
- /* CL=4 */
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
- mtsdram(DDR0_04, 0x0B030300);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0003C812);
- mtsdram(DDR0_07, 0x00090100);
- mtsdram(DDR0_08, 0x03c80001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x000CC800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x1e000000);
- mtsdram(DDR0_18, 0x1e1e1e1e);
- mtsdram(DDR0_19, 0x1e1e1e1e);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
- mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
-#else
- mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
- mtsdram(DDR0_23, 0x01000000);
- mtsdram(DDR0_24, 0x01010001);
-
- mtsdram(DDR0_26, 0x2D93028A);
- mtsdram(DDR0_27, 0x0784682B);
-
- mtsdram(DDR0_28, 0x00000080);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000008);
-
- mtsdram(DDR0_43, 0x050A0200);
- mtsdram(DDR0_44, 0x00000005);
- mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
- denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- TLB_WORD2_I_ENABLE);
- denali_core_search_data_eye();
- remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
- /*
- * Program tlb entries for this size (dynamic)
- */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
- /*
- * Setup 2nd TLB with same physical address but different virtual address
- * with cache enabled. This is done for fast ECC generation.
- */
- program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * Now after initialization (auto-calibration and ECC generation)
- * remove the TLB entries with caches enabled and program again with
- * desired cache functionality
- */
- remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-#endif /* CONFIG_SPL_BUILD */
-
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
-}
diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig
deleted file mode 100644
index b911dbd..0000000
--- a/configs/lcd4_lwmon5_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_LWMON5=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
deleted file mode 100644
index 0a6da68..0000000
--- a/configs/lwmon5_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_LWMON5=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 87e2b35..2697451 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>
alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 1c74e97..868c512 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -419,8 +419,7 @@ void *video_hw_init (void)
board_disp_init ();
#endif
-#if (defined(CONFIG_LWMON5) || \
- defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
+#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Lamp on */
board_backlight_switch (1);
#endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
deleted file mode 100644
index 513167e..0000000
--- a/include/configs/lwmon5.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * lwmon5.h - configuration for lwmon5 board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Liebherr extra version info
- */
-#define CONFIG_IDENT_STRING " - v2.0"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_LWMON5 1 /* Board is lwmon5 */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_440 1 /* ... PPC440 family */
-
-#ifdef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
-#define CONFIG_HOSTNAME lcd4_lwmon5
-#else
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#define CONFIG_HOSTNAME lwmon5
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
-
-#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
-#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#define CONFIG_BOARD_RESET /* Call board_reset */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_LIME_BASE_0 0xc0000000
-#define CONFIG_SYS_LIME_BASE_1 0xc1000000
-#define CONFIG_SYS_LIME_BASE_2 0xc2000000
-#define CONFIG_SYS_LIME_BASE_3 0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
-
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#endif
-
-/*
- * Initial RAM & stack pointer
- *
- * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
- * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
- * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
- */
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#endif
-/* unused GPT0 COMP reg */
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#define CONFIG_SYS_OCM_SIZE (16 << 10)
-/* 440EPx errata CHIP 11: don't use last 4kbytes */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
-
-/* Additional registers for watchdog timer post test */
-#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
-#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
-#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
-#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
-#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
-#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
-#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
-#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH0 0xFC000000
-#define CONFIG_SYS_FLASH1 0xF8000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM 256
-#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_DDR_ECC /* enable ECC */
-#endif
-
-#ifndef CONFIG_LCD4_LWMON5
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_OCM | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SYSMON | \
- CONFIG_SYS_POST_WATCHDOG | \
- CONFIG_SYS_POST_DSP | \
- CONFIG_SYS_POST_BSPEC1 | \
- CONFIG_SYS_POST_BSPEC2 | \
- CONFIG_SYS_POST_BSPEC3 | \
- CONFIG_SYS_POST_BSPEC4 | \
- CONFIG_SYS_POST_BSPEC5)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
- CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_POST_UART { \
- "UART test", \
- "uart", \
- "This test verifies the UART operation.", \
- POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
- &uart_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_UART \
- }
-
-#define CONFIG_POST_WATCHDOG { \
- "Watchdog timer test", \
- "watchdog", \
- "This test checks the watchdog timer.", \
- POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
- &lwmon5_watchdog_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_WATCHDOG \
- }
-
-#define CONFIG_POST_BSPEC1 { \
- "dsPIC init test", \
- "dspic_init", \
- "This test returns result of dsPIC READY test run earlier.", \
- POST_RAM | POST_ALWAYS, \
- &dspic_init_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC1 \
- }
-
-#define CONFIG_POST_BSPEC2 { \
- "dsPIC test", \
- "dspic", \
- "This test gets result of dsPIC POST and dsPIC version.", \
- POST_RAM | POST_ALWAYS, \
- &dspic_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC2 \
- }
-
-#define CONFIG_POST_BSPEC3 { \
- "FPGA test", \
- "fpga", \
- "This test checks FPGA registers and memory.", \
- POST_RAM | POST_ALWAYS | POST_MANUAL, \
- &fpga_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC3 \
- }
-
-#define CONFIG_POST_BSPEC4 { \
- "GDC test", \
- "gdc", \
- "This test checks GDC registers and memory.", \
- POST_RAM | POST_ALWAYS | POST_MANUAL,\
- &gdc_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC4 \
- }
-
-#define CONFIG_POST_BSPEC5 { \
- "SYSMON1 test", \
- "sysmon1", \
- "This test checks GPIO_62_EPX pin indicating power failure.", \
- POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
- &sysmon1_post_test, \
- NULL, \
- NULL, \
- CONFIG_SYS_POST_BSPEC5 \
- }
-
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_LOGBUFFER
-/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
-#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
-#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
-#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
-#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
-#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
- /* 64 byte page write mode using*/
- /* last 6 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
-#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
-
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
- CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
- CONFIG_SYS_I2C_DSPIC_ADDR, \
- CONFIG_SYS_I2C_DSPIC_2_ADDR, \
- CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
- CONFIG_SYS_I2C_DSPIC_IO_ADDR }
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-#define CONFIG_FIT /* enable FIT image support */
-
-#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
-
-#define CONFIG_PREBOOT "setenv bootdelay 15"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=lwmon5\0" \
- "netdev=eth0\0" \
- "unlock=yes\0" \
- "logversion=2\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};" \
- "run nfsargs addip addtty addmisc;bootm\0" \
- "rootpath=/opt/eldk/ppc_4xxFP\0" \
- "bootfile=/tftpboot/lwmon5/uImage\0" \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC180000\0" \
- "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
- "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
- "cp.b 200000 FFF80000 80000\0" \
- "upd=run load update\0" \
- "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
- "autoscr 200000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 300
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 1
-
-/* Video console */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-
-#ifndef CONFIG_LCD4_LWMON5
-/*
- * USB/EHCI
- */
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
-#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
-#define CONFIG_USB_STORAGE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#ifndef CONFIG_LCD4_LWMON5
-#ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
-#ifndef CONFIG_LCD4_LWMON5
-#ifndef DEBUG
-#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
-#endif
-#define CONFIG_WD_PERIOD 40000 /* in usec */
-#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03000280
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
-
-/* Memory Bank 1 (Lime) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01004380
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01004400
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
-
-/* Memory Bank 3 (FPGA2) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x01004400
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
-
-#define CONFIG_SYS_EBC_CFG 0xb8400000
-
-/*
- * Graphics (Fujitsu Lime)
- */
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
-#if 1 /* 133MHz is not tested enough, use 100MHz for now */
-/* Lime Clock frequency is to set 100MHz */
-#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
-#else
-/* Lime Clock frequency for 133MHz */
-#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
-#endif
-
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
-/*
- * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- * and pixel flare on display when 133MHz was configured. According to
- * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
- * Grade
- */
-#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
-#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
-#else
-#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
-#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
-#endif
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PHY1_RST 12
-#define CONFIG_SYS_GPIO_FLASH_WP 14
-#define CONFIG_SYS_GPIO_PHY0_RST 22
-#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
-#define CONFIG_SYS_GPIO_DSPIC_READY 51
-#define CONFIG_SYS_GPIO_CAN_ENABLE 53
-#define CONFIG_SYS_GPIO_LSB_ENABLE 54
-#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
-#define CONFIG_SYS_GPIO_HIGHSIDE 56
-#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
-#define CONFIG_SYS_GPIO_BOARD_RESET 58
-#define CONFIG_SYS_GPIO_LIME_S 59
-#define CONFIG_SYS_GPIO_LIME_RST 60
-#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
-#define CONFIG_SYS_GPIO_WATCHDOG 63
-
-/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
-#ifdef CONFIG_LCD4_LWMON5
-#define GPIO49_VAL 0
-#else
-#define GPIO49_VAL 1
-#endif
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * SPL related defines
- */
-#ifdef CONFIG_LCD4_LWMON5
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NOR_SUPPORT
-#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
-#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
-#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-/* Place BSS for SPL near end of SDRAM */
-#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
-#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
-
-#define CONFIG_SPL_OS_BOOT
-/* Place patched DT blob (fdt)@this address */
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
-
-#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
-
-/* Settings for real U-Boot to be loaded from NOR flash */
-#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_UBOOT_START 0x01002100
-
-#define CONFIG_SYS_OS_BASE 0xf8000000
-#define CONFIG_SYS_FDT_BASE 0xf87c0000
-#endif
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 4/9] powerpc: ppc4xx: remove p3p440 support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (2 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 3/9] powerpc: ppc4xx: remove lwmon5 support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 5/9] powerpc: ppc4xx: remove pcs440ep support Masahiro Yamada
` (4 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/prodrive/p3p440/Kconfig | 12 --
board/prodrive/p3p440/MAINTAINERS | 6 -
board/prodrive/p3p440/Makefile | 9 --
board/prodrive/p3p440/config.mk | 16 --
board/prodrive/p3p440/init.S | 38 -----
board/prodrive/p3p440/p3p440.c | 177 ----------------------
board/prodrive/p3p440/p3p440.h | 24 ---
configs/p3p440_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/p3p440.h | 302 --------------------------------------
11 files changed, 1 insertion(+), 592 deletions(-)
delete mode 100644 board/prodrive/p3p440/Kconfig
delete mode 100644 board/prodrive/p3p440/MAINTAINERS
delete mode 100644 board/prodrive/p3p440/Makefile
delete mode 100644 board/prodrive/p3p440/config.mk
delete mode 100644 board/prodrive/p3p440/init.S
delete mode 100644 board/prodrive/p3p440/p3p440.c
delete mode 100644 board/prodrive/p3p440/p3p440.h
delete mode 100644 configs/p3p440_defconfig
delete mode 100644 include/configs/p3p440.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 883463a..b2e3110 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -130,9 +130,6 @@ config TARGET_MIP405
config TARGET_PIP405
bool "Support PIP405"
-config TARGET_P3P440
- bool "Support p3p440"
-
config TARGET_XPEDITE1000
bool "Support xpedite1000"
@@ -181,7 +178,6 @@ source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
source "board/pcs440ep/Kconfig"
-source "board/prodrive/p3p440/Kconfig"
source "board/sbc405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"
diff --git a/board/prodrive/p3p440/Kconfig b/board/prodrive/p3p440/Kconfig
deleted file mode 100644
index cf53aac..0000000
--- a/board/prodrive/p3p440/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P3P440
-
-config SYS_BOARD
- default "p3p440"
-
-config SYS_VENDOR
- default "prodrive"
-
-config SYS_CONFIG_NAME
- default "p3p440"
-
-endif
diff --git a/board/prodrive/p3p440/MAINTAINERS b/board/prodrive/p3p440/MAINTAINERS
deleted file mode 100644
index 68fd1a9..0000000
--- a/board/prodrive/p3p440/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-P3P440 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/prodrive/p3p440/
-F: include/configs/p3p440.h
-F: configs/p3p440_defconfig
diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile
deleted file mode 100644
index d62f75d..0000000
--- a/board/prodrive/p3p440/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = p3p440.o
-extra-y += init.o
diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk
deleted file mode 100644
index f18b097..0000000
--- a/board/prodrive/p3p440/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
deleted file mode 100644
index 35b1afa..0000000
--- a/board/prodrive/p3p440/init.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
- tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
- tlbtab_end
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
deleted file mode 100644
index 929e8eb..0000000
--- a/board/prodrive/p3p440/p3p440.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-
-#include "p3p440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void set_led(int color)
-{
- switch (color) {
- case LED_OFF:
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
- break;
-
- case LED_GREEN:
- out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
- break;
-
- case LED_RED:
- out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
- break;
-
- case LED_ORANGE:
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
- break;
- }
-}
-
-static int is_monarch(void)
-{
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
- udelay(1000);
-
- if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
- return 0;
- else
- return 1;
-}
-
-static void wait_for_pci_ready(void)
-{
- /*
- * Configure EREADY_IO as input
- */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
- udelay(1000);
-
- for (;;) {
- if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
- return;
- }
-
-}
-
-int board_early_init_f(void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- reg = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
-
- /*--------------------------------------------------------------------
- * Setup pin multiplexing (GPIO/IRQ...)
- *-------------------------------------------------------------------*/
- mtdcr(CPC0_GPIO, 0x03F01F80);
-
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
- out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
- mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: P3P440");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
-
- if (is_monarch()) {
- puts(", Monarch");
- } else {
- puts(", None-Monarch");
- }
-
- putc('\n');
-
- return (0);
-}
-
-int misc_init_r (void)
-{
- /*
- * Adjust flash start and offset to detected values
- */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Check if only one FLASH bank is available
- */
- if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
- mtebc(PB1CR, 0); /* disable cs */
- mtebc(PB1AP, 0);
- mtebc(PB2CR, 0); /* disable cs */
- mtebc(PB2AP, 0);
- mtebc(PB3CR, 0); /* disable cs */
- mtebc(PB3AP, 0);
- }
-
- return 0;
-}
-
-/*************************************************************************
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- if (is_monarch()) {
- wait_for_pci_ready();
- return 1; /* return 1 for host controller */
- } else {
- return 0; /* return 0 for adapter controller */
- }
-}
-#endif /* defined(CONFIG_PCI) */
diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h
deleted file mode 100644
index a164f95..0000000
--- a/board/prodrive/p3p440/p3p440.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __P3P440_H__
-#define __P3P440_H__
-
-#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11)
-#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18)
-#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20)
-#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21)
-#define CONFIG_SYS_LED_RED (0x80000000 >> 22)
-
-#define LED_OFF 1
-#define LED_GREEN 2
-#define LED_RED 3
-#define LED_ORANGE 4
-
-long int fixed_sdram(void);
-
-#endif /* __P3P440_H__ */
diff --git a/configs/p3p440_defconfig b/configs/p3p440_defconfig
deleted file mode 100644
index 84e683b..0000000
--- a/configs/p3p440_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_P3P440=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 2697451..0a54b71 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>
alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
deleted file mode 100644
index eb14003..0000000
--- a/include/configs/p3p440.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * (C) Copyright 2005-2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * board/config_p3p440.h - configuration for Prodrive P3P440
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_P3P440 1 /* Board is P3P440 */
-#define CONFIG_440GP 1 /* Specifc GP support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
-#define CONFIG_SDRAM_ECC /* enable ECC support */
-#define CONFIG_SYS_SDRAM_TABLE { \
- {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
- {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * I2C RTC
- *----------------------------------------------------------------------*/
-#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (PCF8594C) for environment
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
- /* 8 byte page write mode using */
- /* last 3 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
-
-/*-----------------------------------------------------------------------
- * Default configuration (environment varibles...)
- *----------------------------------------------------------------------*/
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=p3p440\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/p3p440/uImage\0" \
- "kernel_addr=ff800000\0" \
- "ramdisk_addr=ff810000\0" \
- "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "unlock=yes\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0x1c /* PHY address */
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_SNTP
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-
-#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH0 0xFF800000
-#define CONFIG_SYS_FLASH1 0xFF000000
-#define CONFIG_SYS_FLASH2 0xFE800000
-#define CONFIG_SYS_FLASH3 0xFE000000
-#define CONFIG_SYS_USB 0xF0000000
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03050200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x03050200
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x03050200
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x03050200
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 7 (USB controller) initialization */
-#define CONFIG_SYS_EBC_PB7AP 0x02015000
-#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 5/9] powerpc: ppc4xx: remove pcs440ep support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (3 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 4/9] powerpc: ppc4xx: remove p3p440 support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 6/9] powerpc: ppc4xx: remove sbc405 support Masahiro Yamada
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/pcs440ep/Kconfig | 9 -
board/pcs440ep/MAINTAINERS | 6 -
board/pcs440ep/Makefile | 9 -
board/pcs440ep/config.mk | 23 --
board/pcs440ep/flash.c | 607 --------------------------------
board/pcs440ep/init.S | 56 ---
board/pcs440ep/pcs440ep.c | 755 ----------------------------------------
configs/pcs440ep_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/pcs440ep.h | 457 ------------------------
11 files changed, 1 insertion(+), 1930 deletions(-)
delete mode 100644 board/pcs440ep/Kconfig
delete mode 100644 board/pcs440ep/MAINTAINERS
delete mode 100644 board/pcs440ep/Makefile
delete mode 100644 board/pcs440ep/config.mk
delete mode 100644 board/pcs440ep/flash.c
delete mode 100644 board/pcs440ep/init.S
delete mode 100644 board/pcs440ep/pcs440ep.c
delete mode 100644 configs/pcs440ep_defconfig
delete mode 100644 include/configs/pcs440ep.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index b2e3110..e379a6f 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,9 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_PCS440EP
- bool "Support pcs440ep"
-
config TARGET_SBC405
bool "Support sbc405"
@@ -177,7 +174,6 @@ source "board/gdsys/intip/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
-source "board/pcs440ep/Kconfig"
source "board/sbc405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"
diff --git a/board/pcs440ep/Kconfig b/board/pcs440ep/Kconfig
deleted file mode 100644
index 5b280f6..0000000
--- a/board/pcs440ep/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PCS440EP
-
-config SYS_BOARD
- default "pcs440ep"
-
-config SYS_CONFIG_NAME
- default "pcs440ep"
-
-endif
diff --git a/board/pcs440ep/MAINTAINERS b/board/pcs440ep/MAINTAINERS
deleted file mode 100644
index 6eccc85..0000000
--- a/board/pcs440ep/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PCS440EP BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/pcs440ep/
-F: include/configs/pcs440ep.h
-F: configs/pcs440ep_defconfig
diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile
deleted file mode 100644
index 4fc24d6..0000000
--- a/board/pcs440ep/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pcs440ep.o flash.o
-extra-y += init.o
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
deleted file mode 100644
index b90d5d0..0000000
--- a/board/pcs440ep/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# PCS440EP board
-#
-
-# Check the U-Boot Image with a SHA1 checksum
-ALL-y += u-boot.sha1
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c
deleted file mode 100644
index 8c5e94f..0000000
--- a/board/pcs440ep/flash.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#ifndef CONFIG_SYS_FLASH_READ0
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * Functions
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-
-unsigned long flash_init(void)
-{
- unsigned long size_b0, size_b1;
- int i;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- base_b0 = FLASH_BASE0_PRELIM;
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- base_b1 = FLASH_BASE1_PRELIM;
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- return (size_b0 + size_b1);
-}
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("ST Micro"); break;
- case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
- case FLASH_MAN_MX: printf ("MXIC "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
- break;
- case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
-
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
- short i;
- short n;
- volatile CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
- value = addr2[CONFIG_SYS_FLASH_READ0];
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
- info->flash_id = FLASH_MAN_EXCEL;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT:
- info->flash_id = FLASH_MAN_MX;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 0.5 MB */
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 0,5 MB */
- break;
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
- info->flash_id += FLASH_SST020;
- info->sector_count = 64;
- info->size = 0x00040000;
- break; /* => 256 kB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
- info->flash_id += FLASH_SST040;
- info->sector_count = 128;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00001000);
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (i < info->sector_count) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf ("- missing\n");
- else
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect)
- if (info->protect[sect])
- prot++;
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- else
- printf ("\n");
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- flag = 0;
- }
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
- (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- } else {
- if (sect == s_first) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- }
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i)
- data = (data << 8) | *src++;
- if ((rc = write_word(info, wp, data)) != 0)
- return (rc);
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0)
- return (0);
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- return (write_word(info, wp, data));
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
- ulong start;
- int flag;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data)
- return (2);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- }
-
- return (0);
-}
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
deleted file mode 100644
index c0e83de..0000000
--- a/board/pcs440ep/init.S
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR detection
- * routine.
- */
-
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
-
- /* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
-
- /* USB 2.0 Device */
- tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
-
- tlbtab_end
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
deleted file mode 100644
index 267c001..0000000
--- a/board/pcs440ep/pcs440ep.c
+++ /dev/null
@@ -1,755 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <malloc.h>
-#include <command.h>
-#include <crc.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-#include <status_led.h>
-#include <u-boot/sha1.h>
-#include <asm/io.h>
-#include <net.h>
-#include <ata.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-unsigned char sha1_checksum[SHA1_SUM_LEN];
-
-/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
-unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
- 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
-
-static void set_leds (int val)
-{
- out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
-}
-
-#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
-
-void __led_init (led_id_t mask, int state)
-{
- int val = GET_LEDS;
-
- if (state == STATUS_LED_ON)
- val |= mask;
- else
- val &= ~mask;
- set_leds (val);
-}
-
-void __led_set (led_id_t mask, int state)
-{
- int val = GET_LEDS;
-
- if (state == STATUS_LED_ON)
- val |= mask;
- else if (state == STATUS_LED_OFF)
- val &= ~mask;
- set_leds (val);
-}
-
-void __led_toggle (led_id_t mask)
-{
- int val = GET_LEDS;
-
- val ^= mask;
- set_leds (val);
-}
-
-static void status_led_blink (void)
-{
- int i;
- int val = GET_LEDS;
-
- /* set all LED which are on, to state BLINKING */
- for (i = 0; i < 4; i++) {
- if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING);
- else status_led_set (3 - i, STATUS_LED_OFF);
- val = val >> 1;
- }
-}
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress (int val)
-{
- /* find all valid Codes for val in README */
- if (val == -BOOTSTAGE_ID_NEED_RESET)
- return;
- if (val < 0) {
- /* smthing goes wrong */
- status_led_blink ();
- return;
- }
- switch (val) {
- case BOOTSTAGE_ID_CHECK_MAGIC:
- /* validating Image */
- status_led_set(0, STATUS_LED_OFF);
- status_led_set(1, STATUS_LED_ON);
- status_led_set(2, STATUS_LED_ON);
- break;
- case BOOTSTAGE_ID_RUN_OS:
- status_led_set(0, STATUS_LED_ON);
- status_led_set(1, STATUS_LED_ON);
- status_led_set(2, STATUS_LED_ON);
- break;
-#if 0
- case BOOTSTAGE_ID_NET_ETH_START:
- /* starting Ethernet configuration */
- status_led_set(0, STATUS_LED_OFF);
- status_led_set(1, STATUS_LED_OFF);
- status_led_set(2, STATUS_LED_ON);
- break;
-#endif
- case BOOTSTAGE_ID_NET_START:
- /* loading Image */
- status_led_set(0, STATUS_LED_ON);
- status_led_set(1, STATUS_LED_OFF);
- status_led_set(2, STATUS_LED_ON);
- break;
- }
-}
-#endif
-
-int board_early_init_f(void)
-{
- register uint reg;
-
- set_leds(0); /* display boot info counter */
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- reg = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
-
- /*--------------------------------------------------------------------
- * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
- * via define from board config file.
- *-------------------------------------------------------------------*/
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
- mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
- * Setup other serial configuration
- *-------------------------------------------------------------------*/
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */
- mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
-
- return 0;
-}
-
-#define EEPROM_LEN 256
-static void load_ethaddr(void)
-{
- int ok_ethaddr, ok_eth1addr;
- int ret;
- uchar buf[EEPROM_LEN];
- char *use_eeprom;
- u16 checksumcrc16 = 0;
-
- /* If the env is sane, then nothing for us to do */
- ok_ethaddr = eth_getenv_enetaddr("ethaddr", buf);
- ok_eth1addr = eth_getenv_enetaddr("eth1addr", buf);
- if (ok_ethaddr && ok_eth1addr)
- return;
-
- /* read the MACs from EEprom */
- status_led_set (0, STATUS_LED_ON);
- status_led_set (1, STATUS_LED_ON);
- ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, buf, EEPROM_LEN);
- if (ret == 0) {
- checksumcrc16 = cyg_crc16 (buf, EEPROM_LEN - 2);
- /* check, if the EEprom is programmed:
- * - The Prefix(Byte 0,1,2) is equal to "ATR"
- * - The checksum, stored in the last 2 Bytes, is correct
- */
- if ((strncmp ((char *)buf,"ATR",3) != 0) ||
- ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
- ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
- /* EEprom is not programmed */
- printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
- } else {
- /* get the MACs */
- if (!ok_ethaddr)
- eth_setenv_enetaddr("ethaddr", &buf[3]);
- if (!ok_eth1addr)
- eth_setenv_enetaddr("eth1addr", &buf[9]);
- return;
- }
- }
-
- /* some error reading the EEprom */
- if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
- /* dont use bootcmd */
- setenv("bootdelay", "-1");
- return;
- }
- /* == default ? use standard */
- if (strncmp (use_eeprom, "default", 7) == 0) {
- return;
- }
- /* Env doesnt exist -> hang */
- status_led_blink ();
- /* here we do this "handy" because we have no interrupts
- at this time */
- puts ("### EEPROM ERROR ### Please RESET the board ###\n");
- for (;;) {
- __led_toggle (12);
- udelay (100000);
- }
- return;
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-struct kbd_data_t {
- char s1;
- char s2;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- char *val;
- unsigned long tmp;
-
- /* use the DIPs for some bootoptions */
- val = getenv (ENV_NAME_DIP);
- tmp = simple_strtoul (val, NULL, 16);
-
- kbd_data->s2 = (tmp & 0x0f);
- kbd_data->s1 = (tmp & 0xf0) >> 4;
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s1) return -1;
-
- s1 = str[1];
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s2) return -1;
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
- if (compare_magic (kbd_data, getenv (magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-static int pcs440ep_readinputs (void)
-{
- int i;
- char value[20];
-
- /* read the inputs and set the Envvars */
- /* Revision Level Bit 26 - 29 */
- i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
- i = swapbits[i];
- sprintf (value, "%02x", i);
- setenv (ENV_NAME_REVLEV, value);
- /* Solder Switch Bit 30 - 33 */
- i = (in32 (GPIO0_IR) & 0x00000003) << 2;
- i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
- i = swapbits[i];
- sprintf (value, "%02x", i);
- setenv (ENV_NAME_SOLDER, value);
- /* DIP Switch Bit 49 - 56 */
- i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
- i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
- sprintf (value, "%02x", i);
- setenv (ENV_NAME_DIP, value);
- return 0;
-}
-
-
-#if defined(CONFIG_SHA1_CHECK_UB_IMG)
-/*************************************************************************
- * calculate a SHA1 sum for the U-Boot image in Flash.
- *
- ************************************************************************/
-static int pcs440ep_sha1 (int docheck)
-{
- unsigned char *data;
- unsigned char *ptroff;
- unsigned char output[20];
- unsigned char org[20];
- int i, len = CONFIG_SHA1_LEN;
-
- memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
- data = (unsigned char *)CONFIG_SYS_LOAD_ADDR;
- ptroff = &data[len + SHA1_SUM_POS];
-
- for (i = 0; i < SHA1_SUM_LEN; i++) {
- org[i] = ptroff[i];
- ptroff[i] = 0;
- }
-
- sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
-
- if (docheck == 2) {
- for (i = 0; i < 20 ; i++) {
- printf("%02X ", output[i]);
- }
- printf("\n");
- }
- if (docheck == 1) {
- for (i = 0; i < 20 ; i++) {
- if (org[i] != output[i]) return 1;
- }
- }
- return 0;
-}
-
-/*************************************************************************
- * do some checks after the SHA1 checksum from the U-Boot Image was
- * calculated.
- *
- ************************************************************************/
-static void pcs440ep_checksha1 (void)
-{
- int ret;
- char *cs_test;
-
- status_led_set (0, STATUS_LED_OFF);
- status_led_set (1, STATUS_LED_OFF);
- status_led_set (2, STATUS_LED_ON);
- ret = pcs440ep_sha1 (1);
- if (ret == 0) return;
-
- if ((cs_test = getenv ("cs_test")) == NULL) {
- /* Env doesnt exist -> hang */
- status_led_blink ();
- /* here we do this "handy" because we have no interrupts
- at this time */
- puts ("### SHA1 ERROR ### Please RESET the board ###\n");
- for (;;) {
- __led_toggle (2);
- udelay (100000);
- }
- }
-
- if (strncmp (cs_test, "off", 3) == 0) {
- printf ("SHA1 U-Boot sum NOT ok!\n");
- setenv ("bootdelay", "-1");
- }
-}
-#else
-static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
-#endif
-
-int misc_init_r (void)
-{
- uint pbcr;
- int size_val = 0;
-
- load_ethaddr();
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[1]);
-
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[1]);
-
- pcs440ep_readinputs ();
- pcs440ep_checksha1 ();
-#ifdef CONFIG_PREBOOT
- {
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
- }
-#endif /* CONFIG_PREBOOT */
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: PCS440EP");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-void spd_ddr_init_hang (void)
-{
- status_led_set (0, STATUS_LED_OFF);
- status_led_set (1, STATUS_LED_ON);
- /* we cannot use hang() because we are still running from
- Flash, and so the status_led driver is not initialized */
- puts ("### SDRAM ERROR ### Please RESET the board ###\n");
- for (;;) {
- __led_toggle (4);
- udelay (100000);
- }
-}
-
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-
- status_led_set (0, STATUS_LED_ON);
- status_led_set (1, STATUS_LED_OFF);
- dram_size = spd_sdram();
- status_led_set (0, STATUS_LED_OFF);
- status_led_set (1, STATUS_LED_ON);
- if (dram_size == 0) {
- hang();
- }
-
- return dram_size;
-}
-
-/*************************************************************************
- * hw_watchdog_reset
- *
- * This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-
-}
-#endif
-
-/*************************************************************************
- * "led" Commando for the U-Boot shell
- *
- ************************************************************************/
-int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 0, i;
- ulong pattern = 0;
-
- pattern = simple_strtoul (argv[1], NULL, 16);
- if (pattern > 0x400) {
- int val = GET_LEDS;
- printf ("led: %x\n", val);
- return rcode;
- }
- if (pattern > 0x200) {
- status_led_blink ();
- hang ();
- return rcode;
- }
- if (pattern > 0x100) {
- status_led_blink ();
- return rcode;
- }
- pattern &= 0x0f;
- for (i = 0; i < 4; i++) {
- if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
- else status_led_set (i, STATUS_LED_OFF);
- pattern = pattern >> 1;
- }
- return rcode;
-}
-
-U_BOOT_CMD(
- led, 2, 1, do_led,
- "set the DIAG-LED",
- "[bitmask] 0x01 = DIAG 1 on\n"
- " 0x02 = DIAG 2 on\n"
- " 0x04 = DIAG 3 on\n"
- " 0x08 = DIAG 4 on\n"
- " > 0x100 set the LED, who are on, to state blinking"
-);
-
-#if defined(CONFIG_SHA1_CHECK_UB_IMG)
-/*************************************************************************
- * "sha1" Commando for the U-Boot shell
- *
- ************************************************************************/
-int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = -1;
-
- if (argc < 2) {
-usage:
- return cmd_usage(cmdtp);
- }
-
- if (argc >= 3) {
- unsigned char *data;
- unsigned char output[20];
- int len;
- int i;
-
- data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
- len = simple_strtoul (argv[2], NULL, 16);
- sha1_csum (data, len, (unsigned char *)output);
- printf ("U-Boot sum:\n");
- for (i = 0; i < 20 ; i++) {
- printf ("%02X ", output[i]);
- }
- printf ("\n");
- if (argc == 4) {
- data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
- memcpy (data, output, 20);
- }
- return 0;
- }
- if (argc == 2) {
- char *ptr = argv[1];
- if (*ptr != '-') goto usage;
- ptr++;
- if ((*ptr == 'c') || (*ptr == 'C')) {
- rcode = pcs440ep_sha1 (1);
- printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
- } else if ((*ptr == 'p') || (*ptr == 'P')) {
- rcode = pcs440ep_sha1 (2);
- } else {
- rcode = pcs440ep_sha1 (0);
- }
- return rcode;
- }
- return rcode;
-}
-
-U_BOOT_CMD(
- sha1, 4, 1, do_sha1,
- "calculate the SHA1 Sum",
- "address len [addr] calculate the SHA1 sum [save@addr]\n"
- " -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
- " -c check the U-Boot image in flash"
-);
-#endif
-
-#if defined (CONFIG_CMD_IDE)
-/* These addresses need to be shifted one place to the left
- * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
- * These values are shifted
- */
-void inline ide_outb(int dev, int port, unsigned char val)
-{
- debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val, (ATA_CURR_BASE(dev)+port));
-
- out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
-}
-unsigned char inline ide_inb(int dev, int port)
-{
- uchar val;
- val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
- debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port, (ATA_CURR_BASE(dev)+port), val);
- return (val);
-}
-#endif
-
-#ifdef CONFIG_IDE_PREINIT
-int ide_preinit (void)
-{
- /* Set True IDE Mode */
- out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
- out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
- out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
- udelay (100000);
- return 0;
-}
-#endif
-
-#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
- if (idereset == 0) {
- out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
- } else {
- out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
- }
- udelay (10000);
-}
-#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
-
-
-/* this is motly the same as it should, causing a little code duplication */
-#if defined(CONFIG_CMD_IDE)
-#define EIEIO __asm__ volatile ("eieio")
-
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- volatile ushort *pbuf =
- (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- ushort *dbuf = (ushort *) sect_buf;
-
- debug("in input swap data base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (words--) {
- *dbuf++ = *pbuf;
- *dbuf++ = *pbuf;
- }
-}
-
-void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
- while (words--) {
- EIEIO;
- *pbuf = ld_le16(dbuf++);
- EIEIO;
- *pbuf = ld_le16(dbuf++);
- }
-}
-
-void ide_input_data(int dev, ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
-
- debug("in input data base for read is %lx\n", (unsigned long) pbuf);
-
- while (words--) {
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
- }
-}
-
-#endif
diff --git a/configs/pcs440ep_defconfig b/configs/pcs440ep_defconfig
deleted file mode 100644
index b01f63a..0000000
--- a/configs/pcs440ep_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PCS440EP=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0a54b71..f535762 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
deleted file mode 100644
index 77e20cf..0000000
--- a/include/configs/pcs440ep.h
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * pcs440ep.h - configuration for PCS440EP board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
-#define CONFIG_440EP 1 /* Specific PPC440EP support */
-#define CONFIG_440 1 /* ... PPC440 family */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
-#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE 0x50000000
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_OVERWRITE 1
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#define ENV_NAME_REVLEV "revision_level"
-#define ENV_NAME_SOLDER "solder_switch"
-#define ENV_NAME_DIP "dip"
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#undef CONFIG_DDR_ECC /* don't use ECC */
-#define SPD_EEPROM_ADDRESS {0x50}
-#define CONFIG_PROG_SDRAM_TLB 1
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=pcs440ep\0" \
- "use_eeprom_ethaddr=default\0" \
- "cs_test=off\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/pcs440ep/uImage\0" \
- "kernel_addr=FFF00000\0" \
- "ramdisk_addr=FFF00000\0" \
- "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
- "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
- "cp.b 100000 FFFA0000 60000\0" \
- "upd=run load update\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-/* check U-Boot image with SHA1 sum */
-#define CONFIG_SHA1_CHECK_UB_IMG 1
-#define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN
-
-/*-----------------------------------------------------------------------
- * Definitions for status LED
- */
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED 1
-
-#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
-#define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
-#define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
-#define STATUS_LED_STATE1 STATUS_LED_ON
-#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
-#define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
-#define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
-#define STATUS_LED_STATE3 STATUS_LED_OFF
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 2
-
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG /* watchdog */
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_REISER
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI 1 /* support kdi files */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
-
-#define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM
-#define CONFIG_SYS_SRAM 0xF1000000
-#define CONFIG_SYS_FPGA 0xF2000000
-#define CONFIG_SYS_CF1 0xF0000000
-#define CONFIG_SYS_CF2 0xF0100000
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 1 (SRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 3 (CompactFlash) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x080BD400
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (CompactFlash) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x080BD400
-#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
-{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
-
-#define CONFIG_IDE_PREINIT 1
-#define CONFIG_IDE_RESET 1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0000)
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 6/9] powerpc: ppc4xx: remove sbc405 support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (4 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 5/9] powerpc: ppc4xx: remove pcs440ep support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 7/9] powerpc: ppc4xx: remove zeus support Masahiro Yamada
` (2 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/sbc405/Kconfig | 9 -
board/sbc405/MAINTAINERS | 6 -
board/sbc405/Makefile | 8 -
board/sbc405/sbc405.c | 91 -----
board/sbc405/strataflash.c | 774 ----------------------------------------
configs/sbc405_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/sbc405.h | 252 -------------
9 files changed, 1 insertion(+), 1148 deletions(-)
delete mode 100644 board/sbc405/Kconfig
delete mode 100644 board/sbc405/MAINTAINERS
delete mode 100644 board/sbc405/Makefile
delete mode 100644 board/sbc405/sbc405.c
delete mode 100644 board/sbc405/strataflash.c
delete mode 100644 configs/sbc405_defconfig
delete mode 100644 include/configs/sbc405.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index e379a6f..16c049e 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,9 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_SBC405
- bool "Support sbc405"
-
config TARGET_T3CORP
bool "Support t3corp"
@@ -174,7 +171,6 @@ source "board/gdsys/intip/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
-source "board/sbc405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"
source "board/xilinx/ml507/Kconfig"
diff --git a/board/sbc405/Kconfig b/board/sbc405/Kconfig
deleted file mode 100644
index 4e7e843..0000000
--- a/board/sbc405/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC405
-
-config SYS_BOARD
- default "sbc405"
-
-config SYS_CONFIG_NAME
- default "sbc405"
-
-endif
diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS
deleted file mode 100644
index 2abad25..0000000
--- a/board/sbc405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SBC405 BOARD
-#M: -
-S: Maintained
-F: board/sbc405/
-F: include/configs/sbc405.h
-F: configs/sbc405_defconfig
diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile
deleted file mode 100644
index 3f2b0e2..0000000
--- a/board/sbc405/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = sbc405.o strataflash.o
diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
deleted file mode 100644
index cafc844..0000000
--- a/board/sbc405/sbc405.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2001
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-#include <spd_sdram.h>
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000);
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
-int misc_init_r (void)
-{
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming sbc405");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 64 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c
deleted file mode 100644
index 7ddc97c..0000000
--- a/board/sbc405/strataflash.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp at seranoa.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-
-#define FLASH_MAN_CFI 0x01000000
-
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char * cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
- (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CONFIG_SYS_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CONFIG_SYS_FLASH_INCREMENT;
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
- flash_info[0].size, flash_info[i].size<<20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
- for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#else
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- - CONFIG_SYS_MONITOR_LEN,
- - 1, &flash_info[1]);
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if( info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3 ), (info->chipwidth << 3 ));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for(i=0;i<aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
-
- for(; (i< info->portwidth) && (cnt > 0) ; i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while(cnt >= info->portwidth) {
- i = info->buffer_size > cnt? cnt: info->buffer_size;
- if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -=i;
- }
-#else
- /* handle the aligned part */
- while(cnt >= info->portwidth) {
- cword.l = 0;
- for(i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i<info->portwidth; ++i, ++cp) {
- flash_add_byte(info, & cword, (*(uchar *)cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if(prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
- prot?"protect":"unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if(prot == 0) {
- int i;
- for(i = 0 ; i<info->sector_count; i++) {
- if(info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
- if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
- printf("Command Sequence Error.\n");
- } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
- int i;
- uchar *cp = (uchar *)cmdbuf;
- for(i=0; i< info->portwidth; i++)
- *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
- info->portwidth <<= 1) {
- for(info->chipwidth =FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
- return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t * info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- if(flash_detect_cfi(info)){
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
- sect_cnt = 0;
- sector = base;
- for(i = 0 ; i < num_erase_regions; i++) {
- if(i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) +1;
- for(j = 0; j< erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if(!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if(flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
- int sector;
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *)dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar)cnt-1);
- while(cnt-- > 0) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/configs/sbc405_defconfig b/configs/sbc405_defconfig
deleted file mode 100644
index 0bc0ab2..0000000
--- a/configs/sbc405_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SBC405=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index f535762..c958601 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+sbc405 powerpc ppc4xx - -
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
deleted file mode 100644
index b2adea9..0000000
--- a/include/configs/sbc405.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * (C) Copyright 2001
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
-
-#define CONFIG_RAMBOOT \
- "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOT \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm ffc00000"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
-
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
- "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
- "f=0x08 tn=sbc405 o=emac \0" \
- "env_startaddr=FF000000\0" \
- "env_endaddr=FF03FFFF\0" \
- "loadfile=vxWorks.st\0" \
- "loadaddr=0x01000000\0" \
- "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
- "uboot_startaddr=FFFC0000\0" \
- "uboot_endaddr=FFFFFFFF\0" \
- "update=tftp ${loadaddr} u-boot.bin;" \
- "protect off ${uboot_startaddr} ${uboot_endaddr};" \
- "era ${uboot_startaddr} ${uboot_endaddr};" \
- "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
- "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
- "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
- "era ${env_startaddr} ${env_endaddr};" \
- "protect on ${env_startaddr} ${env_endaddr}\0"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_ENV_OVERWRITE
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-#define CONFIG_IPADDR 192.168.193.102
-#define CONFIG_NETMASK 255.255.255.224
-#define CONFIG_SERVERIP 192.168.193.119
-#define CONFIG_GATEWAYIP 192.168.193.97
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
-#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0 /* starting right@the beginning */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 7/9] powerpc: ppc4xx: remove zeus support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (5 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 6/9] powerpc: ppc4xx: remove sbc405 support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot,v2,7/9] " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 8/9] powerpc: mpc5xx: remove cmi_mpc5xx support Masahiro Yamada
2015-09-02 1:40 ` [U-Boot] [PATCH v2 9/9] powerpc: mpc85xx: remove stxgp3, stxssa support Masahiro Yamada
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
arch/powerpc/cpu/ppc4xx/start.S | 15 --
board/zeus/Kconfig | 9 -
board/zeus/MAINTAINERS | 6 -
board/zeus/Makefile | 8 -
board/zeus/README | 73 -------
board/zeus/update.c | 89 ---------
board/zeus/zeus.c | 410 ----------------------------------------
configs/zeus_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/zeus.h | 350 ----------------------------------
11 files changed, 1 insertion(+), 968 deletions(-)
delete mode 100644 board/zeus/Kconfig
delete mode 100644 board/zeus/MAINTAINERS
delete mode 100644 board/zeus/Makefile
delete mode 100644 board/zeus/README
delete mode 100644 board/zeus/update.c
delete mode 100644 board/zeus/zeus.c
delete mode 100644 configs/zeus_defconfig
delete mode 100644 include/configs/zeus.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 16c049e..23ecc89 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -11,9 +11,6 @@ choice
config TARGET_T3CORP
bool "Support t3corp"
-config TARGET_ZEUS
- bool "Support zeus"
-
config TARGET_ACADIA
bool "Support acadia"
@@ -176,6 +173,5 @@ source "board/xes/xpedite1000/Kconfig"
source "board/xilinx/ml507/Kconfig"
source "board/xilinx/ppc405-generic/Kconfig"
source "board/xilinx/ppc440-generic/Kconfig"
-source "board/zeus/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 7a0f0d2..77d4040 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -1805,21 +1805,6 @@ ppc405ep_init:
bne _pci_66mhz
#endif /* CONFIG_TAIHU */
-#if defined(CONFIG_ZEUS)
- mfdcr r4, CPC0_BOOT
- andi. r5, r4, CPC0_BOOT_SEP at l
- bne strap_1 /* serial eeprom present */
- lis r3,0x0000
- addi r3,r3,0x3030
- lis r4,0x8042
- addi r4,r4,0x223e
- b 1f
-strap_1:
- mfdcr r3, CPC0_PLLMR0
- mfdcr r4, CPC0_PLLMR1
- b 1f
-#endif
-
addis r3,0,PLLMR0_DEFAULT at h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT at l /* */
addis r4,0,PLLMR1_DEFAULT at h /* PLLMR1 default value */
diff --git a/board/zeus/Kconfig b/board/zeus/Kconfig
deleted file mode 100644
index 6779650..0000000
--- a/board/zeus/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ZEUS
-
-config SYS_BOARD
- default "zeus"
-
-config SYS_CONFIG_NAME
- default "zeus"
-
-endif
diff --git a/board/zeus/MAINTAINERS b/board/zeus/MAINTAINERS
deleted file mode 100644
index 3118710..0000000
--- a/board/zeus/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ZEUS BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/zeus/
-F: include/configs/zeus.h
-F: configs/zeus_defconfig
diff --git a/board/zeus/Makefile b/board/zeus/Makefile
deleted file mode 100644
index aa3658a..0000000
--- a/board/zeus/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = zeus.o update.o
diff --git a/board/zeus/README b/board/zeus/README
deleted file mode 100644
index 1848d8c..0000000
--- a/board/zeus/README
+++ /dev/null
@@ -1,73 +0,0 @@
-
-Storage of the board specific values (ethaddr...)
--------------------------------------------------
-
-The board specific environment variables that should be unique
-for each individual board, can be stored in the I2C EEPROM. This
-will be done from offset 0x80 with the length of 0x80 bytes. The
-following command can be used to store the values here:
-
-=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
-
- ethaddr eth1addr serial#
-
-Now those 3 values are stored into the I2C EEPROM. A CRC is added
-to make sure that the values get not corrupted.
-
-
-SW-Reset Pushbutton handling:
------------------------------
-
-The SW-reset push button is connected to a GPIO input too. This
-way U-Boot can "see" how long the SW-reset was pressed, and a
-specific action can be taken. Two different actions are supported:
-
-a) Release after more than 5 seconds and less then 10 seconds:
- -> Run POST
-
- Please note, that the POST test will take a while (approx. 1 min
- on the 128MByte board). This is mainly due to the system memory
- test.
-
-b) Release after more than 10 seconds:
- -> Restore factory default settings
-
- The factory default values are restored. The default environment
- variables are restored (ipaddr, serverip...) and the board
- specific values (ethaddr, eth1addr and serial#) are restored
- to the environment from the I2C EEPROM. Also a bootline parameter
- is added to the Linux bootline to signal the Linux kernel upon
- the next startup, that the factory defaults should be restored.
-
-The command to check this sw-reset status and act accordingly is
-
-=> chkreset
-
-This command is added to the default "bootcmd", so that it is called
-automatically upon startup.
-
-Also, the 2 LED's are used to indicate the current status of this
-command (time passed since pushing the button). When the POST test
-will be run, the green LED will be switched off, and when the
-factory restore will be initiated, the reg LED will be switched off.
-
-
-Loggin of POST results:
------------------------
-
-The results of the POST tests are logged in a logbuffer located at the end
-of the onboard memory. It can be accessed with the U-Boot command "log":
-
-=> log show
-<4>POST memory PASSED
-<4>POST cache PASSED
-<4>POST cpu PASSED
-<4>POST uart PASSED
-<4>POST ethernet PASSED
-
-The DENX Linux kernel tree has support for this log buffer included. Exactly
-this buffer is used for logging of all kernel messages too. By enabling the
-compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
-can access the U-Boot log messages from Linux too.
-
-2007-08-10, Stefan Roese <sr@denx.de>
diff --git a/board/zeus/update.c b/board/zeus/update.c
deleted file mode 100644
index ac738ef..0000000
--- a/board/zeus/update.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <i2c.h>
-
-#if defined(CONFIG_ZEUS)
-
-u8 buf_zeus_ce[] = {
-/*00 01 02 03 04 05 06 07 */
- 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*08 09 0a 0b 0c 0d 0e 0f */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*10 11 12 13 14 15 16 17 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*18 19 1a 1b 1c 1d 1e 1f */
- 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
-
-u8 buf_zeus_pe[] = {
-
-/* CPU_CLOCK_DIV 1 = 00
- CPU_PLB_FREQ_DIV 3 = 10
- OPB_PLB_FREQ_DIV 2 = 01
- EBC_PLB_FREQ_DIV 2 = 00
- MAL_PLB_FREQ_DIV 1 = 00
- PCI_PLB_FRQ_DIV 3 = 10
- PLL_PLLOUTA = IS SET
- PLL_OPERATING = IS NOT SET
- PLL_FDB_MUL 10 = 1010
- PLL_FWD_DIV_A 3 = 101
- PLL_FWD_DIV_B 3 = 101
- TUNE = 0x2be */
-/*00 01 02 03 04 05 06 07 */
- 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*08 09 0a 0b 0c 0d 0e 0f */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*10 11 12 13 14 15 16 17 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/*18 19 1a 1b 1c 1d 1e 1f */
- 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
-
-static int update_boot_eeprom(void)
-{
- u32 len = 0x20;
- u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
- u8 *pbuf;
- u8 base;
- int i;
-
- if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
- pbuf = buf_zeus_pe;
- base = 0x40;
- } else {
- pbuf = buf_zeus_ce;
- base = 0x00;
- }
-
- for (i = 0; i < len; i++, base++) {
- if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
- printf("i2c_write fail\n");
- return 1;
- }
- udelay(11000);
- }
-
- return 0;
-}
-
-int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
-{
- return update_boot_eeprom();
-}
-
-U_BOOT_CMD (
- update_boot_eeprom, 1, 1, do_update_boot_eeprom,
- "update boot eeprom content",
- ""
-);
-
-#endif
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
deleted file mode 100644
index e2b12f6..0000000
--- a/board/zeus/zeus.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <environment.h>
-#include <logbuff.h>
-#include <post.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define REBOOT_MAGIC 0x07081967
-#define REBOOT_NOP 0x00000000
-#define REBOOT_DO_POST 0x00000001
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-ulong flash_get_size(ulong base, int banknum);
-void env_crc_update(void);
-
-static u32 start_time;
-
-int board_early_init_f(void)
-{
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000);
- mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
-
- /*
- * Configure CPC0_PCI to enable PerWE as output
- */
- mtdcr(CPC0_PCI, CPC0_PCI_SPE);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 pbcr;
- int size_val = 0;
- u32 post_magic;
- u32 post_val;
-
- post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
- post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
- if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
- /*
- * Set special bootline bootparameter to pass this POST boot
- * mode to Linux to reset the username/password
- */
- setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
-
- /*
- * Normally don't run POST tests, only when enabled
- * via the sw-reset button. So disable further tests
- * upon next bootup here.
- */
- out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
- } else {
- /*
- * Only run POST when initiated via the sw-reset button mechanism
- */
- post_word_store(0);
- }
-
- /*
- * Get current time
- */
- start_time = get_timer(0);
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- mfebc(PB0CR, pbcr);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(PB0CR, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: Zeus-");
-
- if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE))
- puts("PE");
- else
- puts("CE");
-
- puts(" of BulletEndPoint");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- /* both LED's off */
- gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
- gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
- udelay(10000);
- /* and on again */
- gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1);
-
- return (0);
-}
-
-static int default_env_var(char *buf, char *var)
-{
- char *ptr;
- char *val;
-
- /*
- * Find env variable
- */
- ptr = strstr(buf + 4, var);
- if (ptr == NULL) {
- printf("ERROR: %s not found!\n", var);
- return -1;
- }
- ptr += strlen(var) + 1;
-
- /*
- * Now the ethaddr needs to be updated in the "normal"
- * environment storage -> redundant flash.
- */
- val = ptr;
- setenv(var, val);
- printf("Updated %s from eeprom to %s!\n", var, val);
-
- return 0;
-}
-
-static int restore_default(void)
-{
- char *buf;
- char *buf_save;
- u32 crc;
-
- set_default_env("");
-
- gd->env_valid = 1;
-
- /*
- * Read board specific values from I2C EEPROM
- * and set env variables accordingly
- * -> ethaddr, eth1addr, serial#
- */
- buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
- if (buf == NULL) {
- printf("ERROR: malloc() failed\n");
- return -1;
- }
- if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
- (u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
- puts("\nError reading EEPROM!\n");
- } else {
- crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
- if (crc != *(u32 *)buf) {
- printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf);
- return -1;
- }
-
- default_env_var(buf, "ethaddr");
- buf += 8 + 18;
- default_env_var(buf, "eth1addr");
- buf += 9 + 18;
- default_env_var(buf, "serial#");
- }
-
- /*
- * Finally save updated env variables back to flash
- */
- saveenv();
-
- free(buf_save);
-
- return 0;
-}
-
-int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *buf;
- char *buf_save;
- char str[32];
- u32 crc;
- char var[32];
-
- if (argc < 4) {
- puts("ERROR!\n");
- return -1;
- }
-
- buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
- memset(buf, 0, FACTORY_RESET_ENV_SIZE);
-
- strcpy(var, "ethaddr");
- printf("Setting %s to %s\n", var, argv[1]);
- sprintf(str, "%s=%s", var, argv[1]);
- strcpy(buf + 4, str);
- buf += strlen(str) + 1;
-
- strcpy(var, "eth1addr");
- printf("Setting %s to %s\n", var, argv[2]);
- sprintf(str, "%s=%s", var, argv[2]);
- strcpy(buf + 4, str);
- buf += strlen(str) + 1;
-
- strcpy(var, "serial#");
- printf("Setting %s to %s\n", var, argv[3]);
- sprintf(str, "%s=%s", var, argv[3]);
- strcpy(buf + 4, str);
-
- crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
- *(u32 *)buf_save = crc;
-
- if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
- (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
- puts("\nError writing EEPROM!\n");
- return -1;
- }
-
- free(buf_save);
-
- return 0;
-}
-
-U_BOOT_CMD(
- setdef, 4, 1, do_set_default,
- "write board-specific values to EEPROM (ethaddr...)",
- "ethaddr eth1addr serial#\n - write board-specific values to EEPROM"
- );
-
-static inline int sw_reset_pressed(void)
-{
- return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
-}
-
-int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
-{
- int delta;
- int count = 0;
- int post = 0;
- int factory_reset = 0;
-
- if (!sw_reset_pressed()) {
- printf("SW-Reset already high (Button released)\n");
- printf("-> No action taken!\n");
- return 0;
- }
-
- printf("Waiting for SW-Reset button to be released.");
-
- while (1) {
- delta = get_timer(start_time);
- if (!sw_reset_pressed())
- break;
-
- if ((delta > CONFIG_SYS_TIME_POST) && !post) {
- printf("\nWhen released now, POST tests will be started.");
- gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
- post = 1;
- }
-
- if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) {
- printf("\nWhen released now, factory default values"
- " will be restored.");
- gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
- factory_reset = 1;
- }
-
- udelay(1000);
- if (!(count++ % 1000))
- printf(".");
- }
-
-
- printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
-
- if (delta > CONFIG_SYS_TIME_FACTORY_RESET) {
- printf("Starting factory reset value restoration...\n");
-
- /*
- * Restore default setting
- */
- restore_default();
-
- /*
- * Reset the board for default to become valid
- */
- do_reset(NULL, 0, 0, NULL);
-
- return 0;
- }
-
- if (delta > CONFIG_SYS_TIME_POST) {
- printf("Starting POST configuration...\n");
-
- /*
- * Enable POST upon next bootup
- */
- out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC);
- out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST);
- post_bootmode_init();
-
- /*
- * Reset the logbuffer for a clean start
- */
- logbuff_reset();
-
- do_reset(NULL, 0, 0, NULL);
-
- return 0;
- }
-
- return 0;
-}
-
-U_BOOT_CMD (
- chkreset, 1, 1, do_chkreset,
- "Check for status of SW-reset button and act accordingly",
- ""
-);
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- u32 post_magic;
- u32 post_val;
-
- post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
- post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
-
- if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
- return 1;
- else
- return 0;
-}
-#endif /* CONFIG_POST */
diff --git a/configs/zeus_defconfig b/configs/zeus_defconfig
deleted file mode 100644
index da2ff3c..0000000
--- a/configs/zeus_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ZEUS=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c958601..438ac8c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de>
sbc405 powerpc ppc4xx - -
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
deleted file mode 100644
index 2bc4e1a..0000000
--- a/include/configs/zeus.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * zeus.h - configuration for Zeus board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_ZEUS 1 /* Board is Zeus */
-#define CONFIG_405EP 1 /* Specifc 405EP support*/
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
-#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0x01 /* PHY address */
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_PHY_RESET 1
-#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_ETHER)
-
-#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * SDRAM
- *----------------------------------------------------------------------*/
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * The layout of the I2C EEPROM, used for bootstrap setup and for board-
- * specific values, like ethaddr... that can be restored via the sw-reset
- * button
- */
-#define FACTORY_RESET_I2C_EEPROM 0x50
-#define FACTORY_RESET_ENV_OFFS 0x80
-#define FACTORY_RESET_ENV_SIZE 0x80
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
-
-/* extra data in OCM */
-#define CONFIG_SYS_POST_MAGIC \
- (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
-#define CONFIG_SYS_POST_VAL \
- (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash 16M) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x05815600
-#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
-#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
-#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
-#define CONFIG_SYS_GPIO0_ODR 0x00000000
-
-#define CONFIG_SYS_GPIO_SW_RESET 1
-#define CONFIG_SYS_GPIO_ZEUS_PE 12
-#define CONFIG_SYS_GPIO_LED_RED 22
-#define CONFIG_SYS_GPIO_LED_GREEN 23
-
-/* Time in milli-seconds */
-#define CONFIG_SYS_TIME_POST 5000
-#define CONFIG_SYS_TIME_FACTORY_RESET 10000
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/* ENVIRONMENT VARS */
-
-#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
-#define CONFIG_IPADDR 192.168.1.10
-#define CONFIG_SERVERIP 192.168.1.100
-#define CONFIG_GATEWAYIP 192.168.1.100
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "logversion=2\0" \
- "hostname=zeus\0" \
- "netdev=eth0\0" \
- "ethact=ppc_4xx_eth0\0" \
- "netmask=255.255.255.0\0" \
- "ramdisk_size=50000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw" \
- " nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw" \
- " ramdisk_size=${ramdisk_size}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0," \
- "${baudrate}\0" \
- "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
- "run nfsargs addip addtty;bootm\0" \
- "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
- "tftp ${ramdisk_mem_addr} ${file_fs};" \
- "run ramargs addip addtty;" \
- "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
- "rootpath=/target_fs/zeus\0" \
- "kernel_fl_addr=ff000000\0" \
- "kernel_mem_addr=200000\0" \
- "ramdisk_fl_addr=ff300000\0" \
- "ramdisk_mem_addr=4000000\0" \
- "uboot_fl_addr=fffc0000\0" \
- "uboot_mem_addr=100000\0" \
- "file_uboot=/zeus/u-boot.bin\0" \
- "tftp_uboot=tftp 100000 ${file_uboot}\0" \
- "update_uboot=protect off fffc0000 ffffffff;" \
- "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
- "protect on fffc0000 ffffffff\0" \
- "upd_uboot=run tftp_uboot;run update_uboot\0" \
- "file_kernel=/zeus/uImage_ba\0" \
- "tftp_kernel=tftp 100000 ${file_kernel}\0" \
- "update_kernel=protect off ff000000 ff17ffff;" \
- "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
- "upd_kernel=run tftp_kernel;run update_kernel\0" \
- "file_fs=/zeus/rootfs_ba.img\0" \
- "tftp_fs=tftp 100000 ${file_fs}\0" \
- "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
- "cp.b 100000 ff300000 580000\0" \
- "upd_fs=run tftp_fs;run update_fs\0" \
- "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
- "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
- ""
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 8/9] powerpc: mpc5xx: remove cmi_mpc5xx support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (6 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 7/9] powerpc: ppc4xx: remove zeus support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
2015-09-02 1:40 ` [U-Boot] [PATCH v2 9/9] powerpc: mpc85xx: remove stxgp3, stxssa support Masahiro Yamada
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/powerpc/cpu/mpc5xx/Kconfig | 4 -
board/cmi/Kconfig | 9 -
board/cmi/MAINTAINERS | 6 -
board/cmi/Makefile | 8 -
board/cmi/README | 84 -------
board/cmi/cmi.c | 57 -----
board/cmi/flash.c | 501 ----------------------------------------
configs/cmi_mpc5xx_defconfig | 6 -
doc/README.scrapyard | 1 +
include/configs/cmi_mpc5xx.h | 240 -------------------
include/status_led.h | 13 --
11 files changed, 1 insertion(+), 928 deletions(-)
delete mode 100644 board/cmi/Kconfig
delete mode 100644 board/cmi/MAINTAINERS
delete mode 100644 board/cmi/Makefile
delete mode 100644 board/cmi/README
delete mode 100644 board/cmi/cmi.c
delete mode 100644 board/cmi/flash.c
delete mode 100644 configs/cmi_mpc5xx_defconfig
delete mode 100644 include/configs/cmi_mpc5xx.h
diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig
index 5275447..d81bfd2 100644
--- a/arch/powerpc/cpu/mpc5xx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xx/Kconfig
@@ -8,15 +8,11 @@ choice
prompt "Target select"
optional
-config TARGET_CMI_MPC5XX
- bool "Support cmi_mpc5xx"
-
config TARGET_PATI
bool "Support PATI"
endchoice
-source "board/cmi/Kconfig"
source "board/mpl/pati/Kconfig"
endmenu
diff --git a/board/cmi/Kconfig b/board/cmi/Kconfig
deleted file mode 100644
index 6efe6b1..0000000
--- a/board/cmi/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CMI_MPC5XX
-
-config SYS_BOARD
- default "cmi"
-
-config SYS_CONFIG_NAME
- default "cmi_mpc5xx"
-
-endif
diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS
deleted file mode 100644
index 60701bf..0000000
--- a/board/cmi/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CMI BOARD
-#M: -
-S: Maintained
-F: board/cmi/
-F: include/configs/cmi_mpc5xx.h
-F: configs/cmi_mpc5xx_defconfig
diff --git a/board/cmi/Makefile b/board/cmi/Makefile
deleted file mode 100644
index cd3bb0d..0000000
--- a/board/cmi/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := flash.o cmi.o
diff --git a/board/cmi/README b/board/cmi/README
deleted file mode 100644
index 0edd50a..0000000
--- a/board/cmi/README
+++ /dev/null
@@ -1,84 +0,0 @@
-
-Summary:
-========
-
-This file contains information about the cmi board configuration.
-Please see cmi_mpc5xx_config for further details. The cmi board is
-a customer specific board but should work with small modifications
-on every board which has a MPC5xx and either a 28F128J3A,
-28F320J3A or 28F640J3A Intel flash mounted.
-
-Board Discription:
-==================
-
-* Motorola MPC555
-* RS232 connection
-* Intel flash 28F640J3A
-* Micron SRAM 1M
-* Altera PLD
-
-Bootstrap:
-==========
-
-In contrast to the usual boot sequence used in U-Boot, on the
-cmi board we don't boot from the external flash directly.
-Because of we use a 16-bit flash and don't sample a RCW
-from the data bus to set the startup buswidth to 16-bit.
-Unfortunatly the default width, sampled from the default RCW
-is 32-bit. For this reason we burn the proper RCW into the
-internal flash shadow location and boot after power-on or
-reset from the internal flash and then branch to 0x02000100
-where the U-Boot reset vector handler is located.
-
-Memory Map:
-===========
-
-Memory Map after relocation:
-
- 0x0000 0000 CONFIG_SYS_SDRAM_BASE
- :
- 0x000F 9FFF
- :
- :
- 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress)
- :
- 0x0130 7FFF
- :
- :
- 0x0200 0000 CONFIG_SYS_FLASH_BASE
- :
- 0x027C FFFF
- :
- :
- 0x0300 0000 PLD_BASE
-
-Flash Partition:
-
- 0x0200 0000 Block 0 and 1 contain U-Boot except
- : environment
- :
- 0x0201 FFFF
- 0x0202 0000 Block 2 contains environment (.ppcenv)
- :
- 0x0202 FFFF
-
-See README file for futher information about U-Boot relocation
-and partitioning.
-
-Tested Features:
-================
-
-* U-Boot commands: go, loads, loadb, all memory features, printenv,
- setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version,
- coninfo, help (see configuration file for available commands)
-
-* Blinking led to indicate boot process
-
-Added or Changed Files:
-=======================
-
-u-boot-0.2.0/board/cmi/*
-u-boot-0.2.0/include/configs/cmi_mpc5xx.h
-
-Regards,
-Martin
diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c
deleted file mode 100644
index 37028c3..0000000
--- a/board/cmi/cmi.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * File: cmi.c
- *
- * Discription: For generic board specific functions
- *
- */
-
-
-#include <common.h>
-#include <mpc5xx.h>
-
-#define SRAM_SIZE 1024000L /* 1M RAM available*/
-
-#if defined(__APPLE__)
-/* Leading underscore on symbols */
-# define SYM_CHAR "_"
-#else /* No leading character on symbols */
-# define SYM_CHAR
-#endif
-
-/*
- * Macros to generate global absolutes.
- */
-#define GEN_SYMNAME(str) SYM_CHAR #str
-#define GEN_VALUE(str) #str
-#define GEN_ABS(name, value) \
- asm (".globl " GEN_SYMNAME(name)); \
- asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
-
-/*
- * Check the board
- */
-int checkboard(void)
-{
- puts ("Board: ### No HW ID - assuming CMI board\n");
- return (0);
-}
-
-/*
- * Get RAM size.
- */
-phys_size_t initdram(int board_type)
-{
- return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */
-}
-
-/*
- * Absolute environment address for linker file.
- */
-GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/cmi/flash.c b/board/cmi/flash.c
deleted file mode 100644
index d9986f9..0000000
--- a/board/cmi/flash.c
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * File: flash.c
- *
- * Discription: This Driver is for 28F320J3A, 28F640J3A and
- * 28F128J3A Intel flashs working in 16 Bit mode.
- * They are single bank flashs.
- *
- * Most of this code is taken from existing u-boot
- * source code.
- */
-
-
-#include <common.h>
-#include <mpc5xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#define FLASH_ID_MASK 0xFFFF
-#define FLASH_BLOCK_SIZE 0x00010000
-#define FLASH_CMD_READ_ID 0x0090
-#define FLASH_CMD_RESET 0x00ff
-#define FLASH_CMD_BLOCK_ERASE 0x0020
-#define FLASH_CMD_ERASE_CONFIRM 0x00D0
-#define FLASH_CMD_CLEAR_STATUS 0x0050
-#define FLASH_CMD_SUSPEND_ERASE 0x00B0
-#define FLASH_CMD_WRITE 0x0040
-#define FLASH_CMD_PROTECT 0x0060
-#define FLASH_CMD_PROTECT_SET 0x0001
-#define FLASH_CMD_PROTECT_CLEAR 0x00D0
-#define FLASH_STATUS_DONE 0x0080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*
- * Local function prototypes
- */
-static ulong flash_get_size (vu_short *addr, flash_info_t *info);
-static int write_short (flash_info_t *info, ulong dest, ushort data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*
- * Initialize flash
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-#if 1
- debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-#endif
- size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- return size_b0;
-}
-
-/*
- * Compute start adress of each sector (block)
- */
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + i * FLASH_BLOCK_SIZE;
- }
- return;
-
- default:
- printf ("Don't know sector offsets for flash type 0x%lx\n",
- info->flash_id);
- return;
- }
-}
-
-/*
- * Print flash information
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n");
- break;
- case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*
- * Get size of flash in bytes.
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_short *addr, flash_info_t *info)
-{
- vu_short value;
-
- /* Read Manufacturer ID */
- addr[0] = FLASH_CMD_READ_ID;
- value = addr[0];
-
- switch (value) {
- case (AMD_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (SST_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (STM_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = FLASH_CMD_RESET; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 32 MBit */
-
- case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 64 MBit */
-
- case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 128 MBit */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- addr[0] = FLASH_CMD_RESET; /* restore read mode */
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = FLASH_CMD_RESET; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*
- * Erase unprotected sectors
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_short *addr = (vu_short *)(info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#ifdef DEBUG
- printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
-#endif
-
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_BLOCK_ERASE;
- *addr = FLASH_CMD_ERASE_CONFIRM;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash erase timeout at address %lx\n", info->start[sect]);
- *addr = FLASH_CMD_SUSPEND_ERASE;
- *addr = FLASH_CMD_RESET;
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- *addr = FLASH_CMD_RESET;
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- ushort data;
- int i, rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start byte
- */
-
- if (addr - wp) {
- data = 0;
- data = (data << 8) | *src++;
- --cnt;
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
-
- while (cnt >= 2) {
- data = 0;
- for (i=0; i<2; ++i) {
- data = (data << 8) | *src++;
- }
-
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
-
- data = 0;
- for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<2; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_short(info, wp, data));
-
-}
-
-/*
- * Write 16 bit (short) to flash
- */
-
-static int write_short (flash_info_t *info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_short *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- if (!(info->flash_id & FLASH_VENDMASK)) {
- return 4;
- }
- *addr = FLASH_CMD_ERASE_CONFIRM;
- *addr = FLASH_CMD_WRITE;
-
- *((vu_short *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- /* data polling for D7 */
- start = get_timer (0);
-
- /* wait for error or finish */
- while(!(addr[0] & FLASH_STATUS_DONE)){
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- addr[0] = FLASH_CMD_RESET;
- return (1);
- }
- }
-
- *addr = FLASH_CMD_RESET;
- return (0);
-}
-
-/*
- * Protects a flash sector
- */
-
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- vu_short *addr = (vu_short*)(info->start[sector]);
- ulong start;
-
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_PROTECT;
-
- if(prot) {
- *addr = FLASH_CMD_PROTECT_SET;
- } else {
- *addr = FLASH_CMD_PROTECT_CLEAR;
- }
-
- /* wait for error or finish */
- start = get_timer (0);
- while(!(addr[0] & FLASH_STATUS_DONE)){
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash protect timeout at address %lx\n", info->start[sector]);
- addr[0] = FLASH_CMD_RESET;
- return (1);
- }
- }
- /* Set software protect flag */
- info->protect[sector] = prot;
- *addr = FLASH_CMD_RESET;
- return (0);
-}
diff --git a/configs/cmi_mpc5xx_defconfig b/configs/cmi_mpc5xx_defconfig
deleted file mode 100644
index abebfab..0000000
--- a/configs/cmi_mpc5xx_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_PPC=y
-CONFIG_5xx=y
-CONFIG_TARGET_CMI_MPC5XX=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 438ac8c..d97e82f 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+cmi_mpc5xx powerpc mpc5xx - -
zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de>
sbc405 powerpc ppc4xx - -
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
deleted file mode 100644
index d081865..0000000
--- a/include/configs/cmi_mpc5xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * File: cmi_mpc5xx.h
- *
- * Discription: Config header file for cmi
- * board using an MPC5xx CPU
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
-#define CONFIG_CMI 1 /* Using the customized cmi board */
-
-#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */
-
-/* Serial Console Configuration */
-#define CONFIG_5xx_CONS_SCI1
-#undef CONFIG_5xx_CONS_SCI2
-
-#define CONFIG_BAUDRATE 57600
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_ASKENV
-
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
-
-#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
-
-#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
-
-#define CONFIG_STATUS_LED 1 /* Enable status led */
-
-#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
-
-
-/*
- * Low Level Configuration Settings
- */
-
-/*
- * Internal Memory Mapped (This is not the IMMR content)
- */
-#define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
-
-/*
- * Start addresses for the final memory configuration
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
-#define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */
-#define PLD_BASE 0x03000000 /* PLD */
-#define ANYBUS_BASE 0x03010000 /* Anybus Module */
-
-#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
- /* This adress is given to the linker with -Ttext to */
- /* locate the text section at this adress. */
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *-----------------------------------------------------------------------
- *
- */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts@this adress */
-#define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
- SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration
- *-----------------------------------------------------------------------
- * Data show cycle
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register
- *-----------------------------------------------------------------------
- * Set all bits to 40 Mhz
- *
- */
-#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
-#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
-
-
-/*-----------------------------------------------------------------------
- * UMCR - UIMB Module Configuration Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
-
-/*-----------------------------------------------------------------------
- * ICTRL - I-Bus Support Control Register
- */
-#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
-
-/*-----------------------------------------------------------------------
- * USIU - Memory Controller Register
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
-#define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
-#define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE)
-#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
-#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
-#define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
-#define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
- OR_ACS_10 | OR_ETHR | OR_CSNT)
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
-
-/*-----------------------------------------------------------------------
- * DER - Timer Decrementer
- *-----------------------------------------------------------------------
- * Initialise to zero
- */
-#define CONFIG_SYS_DER 0x00000000
-
-#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index a5e35df..f6be181 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -64,19 +64,6 @@ void status_led_set (int led, int state);
* filling this file up with lots of custom board stuff.
*/
-/***** CMI ********************************************************/
-#elif defined(CONFIG_CMI)
-# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr
-# define STATUS_LED_DAT im_mios.mios_mpiosm32dr
-
-# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/
- /* MIOS outputs */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Blinking periode is 500 ms */
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
#elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v2 9/9] powerpc: mpc85xx: remove stxgp3, stxssa support
2015-09-02 1:40 [U-Boot] [PATCH v2 0/9] Janitorial: powerpc: remove PowerPC non-generic boards Masahiro Yamada
` (7 preceding siblings ...)
2015-09-02 1:40 ` [U-Boot] [PATCH v2 8/9] powerpc: mpc5xx: remove cmi_mpc5xx support Masahiro Yamada
@ 2015-09-02 1:40 ` Masahiro Yamada
2015-09-02 21:59 ` [U-Boot] [U-Boot, v2, " Tom Rini
8 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-09-02 1:40 UTC (permalink / raw)
To: u-boot
These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Dan Malek <dan@embeddedalley.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 8 -
board/stx/stxgp3/Kconfig | 12 -
board/stx/stxgp3/MAINTAINERS | 6 -
board/stx/stxgp3/Makefile | 12 -
board/stx/stxgp3/ddr.c | 46 ----
board/stx/stxgp3/flash.c | 499 ---------------------------------------
board/stx/stxgp3/law.c | 42 ----
board/stx/stxgp3/stxgp3.c | 331 --------------------------
board/stx/stxgp3/tlb.c | 114 ---------
board/stx/stxssa/Kconfig | 12 -
board/stx/stxssa/MAINTAINERS | 7 -
board/stx/stxssa/Makefile | 11 -
board/stx/stxssa/ddr.c | 47 ----
board/stx/stxssa/law.c | 44 ----
board/stx/stxssa/stxssa.c | 370 -----------------------------
board/stx/stxssa/tlb.c | 90 -------
configs/stxgp3_defconfig | 5 -
configs/stxssa_4M_defconfig | 5 -
configs/stxssa_defconfig | 5 -
doc/README.scrapyard | 2 +
include/configs/stxgp3.h | 354 ---------------------------
include/configs/stxssa.h | 440 ----------------------------------
22 files changed, 2 insertions(+), 2460 deletions(-)
delete mode 100644 board/stx/stxgp3/Kconfig
delete mode 100644 board/stx/stxgp3/MAINTAINERS
delete mode 100644 board/stx/stxgp3/Makefile
delete mode 100644 board/stx/stxgp3/ddr.c
delete mode 100644 board/stx/stxgp3/flash.c
delete mode 100644 board/stx/stxgp3/law.c
delete mode 100644 board/stx/stxgp3/stxgp3.c
delete mode 100644 board/stx/stxgp3/tlb.c
delete mode 100644 board/stx/stxssa/Kconfig
delete mode 100644 board/stx/stxssa/MAINTAINERS
delete mode 100644 board/stx/stxssa/Makefile
delete mode 100644 board/stx/stxssa/ddr.c
delete mode 100644 board/stx/stxssa/law.c
delete mode 100644 board/stx/stxssa/stxssa.c
delete mode 100644 board/stx/stxssa/tlb.c
delete mode 100644 configs/stxgp3_defconfig
delete mode 100644 configs/stxssa_4M_defconfig
delete mode 100644 configs/stxssa_defconfig
delete mode 100644 include/configs/stxgp3.h
delete mode 100644 include/configs/stxssa.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 3e8d0b1..ae0823a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -137,12 +137,6 @@ config TARGET_CONTROLCENTERD
config TARGET_KMP204X
bool "Support kmp204x"
-config TARGET_STXGP3
- bool "Support stxgp3"
-
-config TARGET_STXSSA
- bool "Support stxssa"
-
config TARGET_XPEDITE520X
bool "Support xpedite520x"
@@ -191,8 +185,6 @@ source "board/gdsys/p1022/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
-source "board/stx/stxgp3/Kconfig"
-source "board/stx/stxssa/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"
diff --git a/board/stx/stxgp3/Kconfig b/board/stx/stxgp3/Kconfig
deleted file mode 100644
index 910b31b..0000000
--- a/board/stx/stxgp3/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_STXGP3
-
-config SYS_BOARD
- default "stxgp3"
-
-config SYS_VENDOR
- default "stx"
-
-config SYS_CONFIG_NAME
- default "stxgp3"
-
-endif
diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS
deleted file mode 100644
index bd5743c..0000000
--- a/board/stx/stxgp3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-STXGP3 BOARD
-#M: Dan Malek <dan@embeddedalley.com>
-S: Orphan (since 2014-06)
-F: board/stx/stxgp3/
-F: include/configs/stxgp3.h
-F: configs/stxgp3_defconfig
diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile
deleted file mode 100644
index 78e2d6c..0000000
--- a/board/stx/stxgp3/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += stxgp3.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += flash.o
-obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
deleted file mode 100644
index 41d4cfe..0000000
--- a/board/stx/stxgp3/ddr.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/stx/stxgp3/flash.c b/board/stx/stxgp3/flash.c
deleted file mode 100644
index 61066a4..0000000
--- a/board/stx/stxgp3/flash.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. <dan@embeddededge.com>
- * Copied from ADS85xx.
- * Updated to support the Silicon Tx GP3 8560. We should only find
- * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash),
- * but I left other code here in case people order custom boards.
- *
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao,(X.Xiao at motorola.com)
- *
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth at lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#undef DEBUG
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
-#ifdef DEBUG
- printf("Check flash at 0x%08x\n",(uint)addr);
-#endif
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
- udelay(20);
- asm("sync");
-
- value = addr[0] & 0x00FF00FF;
-
-#ifdef DEBUG
- printf("manufacturer=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case MT_MANUFACT: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
-#ifdef DEBUG
- printf("deviceID=0x%x\n",(uint)value);
-#endif
- switch (value) {
-
- case (INTEL_ID_28F640C3T):
- info->flash_id += FLASH_28F640C3T;
- info->sector_count = 135;
- info->size = 0x01000000;
- sector_offset = 0x20000;
- break; /* => 2x8 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table
- * The first 127 blocks are large, the last 8 are small.
- */
- for (i = 0; i < 127; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* Sectors are locked upon reset */
- info->protect[i] = 0;
- }
- for (i = 127; i < 135; i++) {
- info->start[i] = base;
- base += 0x4000;
- /* Sectors are locked upon reset */
- info->protect[i] = 0;
- }
-
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- asm("sync");
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-#ifdef DEBUG
- printf("\nFlash Erase:\n");
-#endif
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
- return 1;
- }
-
- /* Start erase on unprotected sectors */
-#if defined(DEBUG)
- printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
-#endif
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
- asm("sync");
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
- /* Single Block Erase Command */
- *addr = 0x20202020;
- asm("sync");
- /* Confirm */
- *addr = 0xD0D0D0D0;
- asm("sync");
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- asm("sync");
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
- while ((*addr & 0x00800080) != 0x00800080) {
- if(*addr & 0x00200020){
- printf("Error in Block Erase - Lock Bit may be set!\n");
- printf("Status Register = 0x%X\n", (uint)*addr);
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
- }
- }
-
- printf ("flash erase done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
- asm("sync");
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
-
- while (((csr = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(vu_long * addr)
-{
- ulong start, now;
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
-
- *addr = 0x60606060;
- asm("sync");
- *addr = 0xd0d0d0d0;
- asm("sync");
-
- start = get_timer (0);
- while((*addr & 0x00800080) != 0x00800080){
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- }
- return 0;
-}
-
-#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c
deleted file mode 100644
index 611fa4b..0000000
--- a/board/stx/stxgp3/law.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xfc00_0000 0xfc00_ffff Config Latch 64K
- * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- /* This is not so much the SDRAM map as it is the whole localbus map. */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
deleted file mode 100644
index c80d525..0000000
--- a/board/stx/stxgp3/stxgp3.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * (C) Copyright 2003, Embedded Edge, LLC
- * Dan Malek, <dan@embeddededge.com>
- * Copied from ADS85xx.
- * Updates for Silicon Tx GP3 8560
- *
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao at motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-static uint64_t next_led_update;
-static uint led_bit;
-
-int
-board_early_init_f(void)
-{
-#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
- pci->peer &= 0xfffffffdf; /* disable master abort */
-#endif
- return 0;
-}
-
-void
-reset_phy(void)
-{
- volatile uint *blatch;
-
- blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
-
- /* reset Giga bit Ethernet port if needed here */
-
- *blatch &= ~0x000000c0;
- udelay(100);
- *blatch = 0x000000c1; /* Light one led, too */
- udelay(1000);
-
-#if 0 /* This is the port we really want to use for debugging. */
- /* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
- bcsr->bcsr2 &= ~FETH2_RST;
- udelay(2);
- bcsr->bcsr2 |= FETH2_RST;
- udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
- bcsr->bcsr3 &= ~FETH3_RST;
- udelay(2);
- bcsr->bcsr3 |= FETH3_RST;
- udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- /* reset PHY */
- miiphy_reset("FCC1", 0x0);
-
- /* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
- bb_miiphy_write(NULL, 0x02, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-#endif
-}
-
-int
-checkboard(void)
-{
- printf ("Board: Silicon Tx GPPP 8560 Board\n");
- return (0);
-}
-
-/* Blinkin' LEDS for Robert.
-*/
-void
-show_activity(int flag)
-{
- volatile uint *blatch;
-
- if (next_led_update > get_ticks())
- return;
-
- blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
-
- led_bit >>= 1;
- if (led_bit == 0)
- led_bit = 0x08;
- *blatch = (0xc0 | led_bit);
- eieio();
- next_led_update += (get_tbclk() / 4);
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_stxgp3_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_stxgp3_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
diff --git a/board/stx/stxgp3/tlb.c b/board/stx/stxgp3/tlb.c
deleted file mode 100644
index 7c877b2..0000000
--- a/board/stx/stxgp3/tlb.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 7: 16K Non-cacheable, guarded
- * 0xfc000000 16K Configuration Latch register
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/stx/stxssa/Kconfig b/board/stx/stxssa/Kconfig
deleted file mode 100644
index bd47b04..0000000
--- a/board/stx/stxssa/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_STXSSA
-
-config SYS_BOARD
- default "stxssa"
-
-config SYS_VENDOR
- default "stx"
-
-config SYS_CONFIG_NAME
- default "stxssa"
-
-endif
diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS
deleted file mode 100644
index b7cc89b..0000000
--- a/board/stx/stxssa/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-STXSSA BOARD
-#M: Dan Malek <dan@embeddedalley.com>
-S: Orphan (since 2014-06)
-F: board/stx/stxssa/
-F: include/configs/stxssa.h
-F: configs/stxssa_defconfig
-F: configs/stxssa_4M_defconfig
diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile
deleted file mode 100644
index b1d4b0a..0000000
--- a/board/stx/stxssa/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += stxssa.o
-obj-y += law.o
-obj-y += tlb.o
-obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
deleted file mode 100644
index 1ccd4c5..0000000
--- a/board/stx/stxssa/ddr.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c
deleted file mode 100644
index 72373f5..0000000
--- a/board/stx/stxssa/law.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf000_0000 0xfaff_ffff Local bus 128M
- * 0xfb00_0000 0xfb00_ffff Config Latch 64K
- * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- /* Map the whole localbus, including flash and reset latch. */
- SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
deleted file mode 100644
index 6e4eed8..0000000
--- a/board/stx/stxssa/stxssa.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * (C) Copyright 2005, Embedded Alley Solutions, Inc.
- * Dan Malek, <dan@embeddedalley.com>
- * Copied from STx GP3.
- * Updates for Silicon Tx GP3 SSA
- *
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao at motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-static uint64_t next_led_update;
-static uint led_bit;
-
-void
-reset_phy(void)
-{
- volatile uint *blatch;
-#if 0
- int i;
-#endif
- blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
-
- /* reset Giga bit Ethernet port if needed here */
-
-#if 1
- *blatch &= ~0x000000c0;
- udelay(100);
-#else
- *blatch = 0;
- asm("eieio");
- for (i=0; i<1000; i++)
- udelay(1000);
-#endif
- *blatch = 0x000000c1; /* Light one led, too */
- udelay(1000);
-
-#if 0 /* This is the port we really want to use for debugging. */
- /* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
- bcsr->bcsr2 &= ~FETH2_RST;
- udelay(2);
- bcsr->bcsr2 |= FETH2_RST;
- udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
- bcsr->bcsr3 &= ~FETH3_RST;
- udelay(2);
- bcsr->bcsr3 |= FETH3_RST;
- udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- /* reset PHY */
- miiphy_reset("FCC1", 0x0);
-
- /* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
- bb_miiphy_write(NULL, 0x02, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-#endif
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup (blob, bd);
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int
-board_early_init_f(void)
-{
-#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
- pci->peer &= 0xffffffdf; /* disable master abort */
-#endif
-
- /* Why is the phy reset done _after_ the ethernet
- * initialization in arch/powerpc/lib/board.c?
- * Do it here so it's done before the TSECs are used.
- */
- reset_phy();
-
- return 0;
-}
-
-int
-checkboard(void)
-{
- printf ("Board: Silicon Tx GPPP SSA Board\n");
- return (0);
-}
-
-/* Blinkin' LEDS for Robert.
-*/
-void
-show_activity(int flag)
-{
- volatile uint *blatch;
-
- if (next_led_update > get_ticks())
- return;
-
- blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
-
- led_bit >>= 1;
- if (led_bit == 0)
- led_bit = 0x08;
- *blatch = (0xc0 | led_bit);
- eieio();
- next_led_update += (get_tbclk() / 4);
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_stxgp3_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
-};
-#endif
-
-
-static struct pci_controller hose[] = {
-#ifndef CONFIG_PCI_PNP
- { config_table: pci_stxgp3_config_table,},
-#else
- {},
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
- pci_mpc85xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Initialize TSECs first */
- return pci_eth_init(bis);
-}
diff --git a/board/stx/stxssa/tlb.c b/board/stx/stxssa/tlb.c
deleted file mode 100644
index 49c630c..0000000
--- a/board/stx/stxssa/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 6M4 FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 6: 256M Non-cacheable, guarded
- * 0xf0000000 Local bus expansion option.
- * 0xfb000000 Configuration Latch register (one word)
- * 0xfc000000 Up to 64M flash
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/stxgp3_defconfig b/configs/stxgp3_defconfig
deleted file mode 100644
index 816092d..0000000
--- a/configs/stxgp3_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_STXGP3=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="GPPP=> "
diff --git a/configs/stxssa_4M_defconfig b/configs/stxssa_4M_defconfig
deleted file mode 100644
index 7547906..0000000
--- a/configs/stxssa_4M_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_STXSSA=y
-CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M"
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/stxssa_defconfig b/configs/stxssa_defconfig
deleted file mode 100644
index ec812c1..0000000
--- a/configs/stxssa_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_STXSSA=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="SSA=> "
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d97e82f..9cda0bd 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+stxgp3 powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com>
+stxssa powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com>
cmi_mpc5xx powerpc mpc5xx - -
zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de>
sbc405 powerpc ppc4xx - -
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
deleted file mode 100644
index 25b7d5f..0000000
--- a/include/configs/stxgp3.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * (C) Copyright 2003 Embedded Edge, LLC
- * Dan Malek <dan@embeddededge.com>
- * Copied from ADS85xx.
- * Updates for Silicon Tx GP3 8560 board.
- *
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
-#define CONFIG_MPC8560 1
-
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support*/
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-/* sysclk for MPC85xx
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
-
-/* Blinkin' LEDs for Robert :-)
-*/
-#define CONFIG_SHOW_ACTIVITY 1
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-
-/* Localbus SDRAM is an option, not all boards have it.
- * This address, however, is used to configure a 256M local bus
- * window that includes the Config latch below.
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
-
-#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* The configuration latch is Chip Select 1.
- * It's an 8-bit latch in the lower 8 bits of the word.
- */
-#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
-#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
-#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
-#endif
-#define CONFIG_SYS_CCSRBAR 0xfdf00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#undef CONFIG_FSL_DDR_INTERACTIVE
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/* local bus definitions */
-#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-
-#if 0
-#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
-#else
-/* I did the 'if 0' so we could keep the syntax above if ever needed. */
-#undef CONFIG_SYS_I2C_NOPROBES
-#endif
-
-/* RapdIO Map configuration, mapped 1:1.
-*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
-
-/* Standard 8560 PCI addressing, mapped 1:1.
-*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
-
-#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII 1 /* MII PHY management */
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 4
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define CONFIG_ETHPRIME "TSEC0"
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
-#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
-#if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#if 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-#else
- #define CONFIG_SYS_FCC_PSMR 0
-#endif
- #define FETH2_RST 0x01
-#elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
-
-/* MDIO is done through the TSEC0 control.
-*/
-#define CONFIG_MII /* MII PHY management */
-#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
-
-#endif
-
-/* Environment */
-/* We use the top boot sector flash, so we have some 16K sectors for env
- */
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
- #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
-#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
-#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_CMD_ELF
-#endif
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_SERVERIP 192.168.85.1
-#define CONFIG_IPADDR 192.168.85.60
-#define CONFIG_GATEWAYIP 192.168.85.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME STX_GP3
-#define CONFIG_ROOTPATH "/gppproot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x1000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
deleted file mode 100644
index ee16fea..0000000
--- a/include/configs/stxssa.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * (C) Copyright 2005 Embedded Alley Solutions, Inc.
- * Dan Malek <dan@embeddedalley.com>
- * Copied from STx GP3.
- * Updates for Silicon Tx GP3 SSA board.
- *
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
-#define CONFIG_MPC8560 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_PCI /* PCI ethernet support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support*/
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-/* sysclk for MPC85xx
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
-
-/* Blinkin' LEDs for Robert :-)
-*/
-#define CONFIG_SHOW_ACTIVITY 1
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-
-/* Localbus connector. There are many options that can be
- * connected here, including sdram or lots of flash.
- * This address, however, is used to configure a 256M local bus
- * window that includes the Config latch below.
- */
-#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
-#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
-
-/* There are various flash options used, we configure for the largest,
- * which is 64Mbytes. The CFI works fine and will discover the proper
- * sizes.
- */
-#ifdef CONFIG_STXSSA_4M
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
-#else
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
-#endif
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/* The configuration latch is Chip Select 1.
- * It's an 8-bit latch in the lower 8 bits of the word.
- */
-#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
-#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
-#endif
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#undef CONFIG_FSL_DDR_INTERACTIVE
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/* local bus definitions */
-#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#undef CONFIG_SYS_I2C_NOPROBES
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/* I2C EEPROM. AT24C32, we keep our environment in here.
-*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/*
- * Standard 8555 PCI mapping.
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
-
-#if defined(CONFIG_PCI) /* PCI Ethernet card */
-#define CONFIG_MPC85XX_PCI2 1
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#define CONFIG_EEPRO100
-#define CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII 1 /* MII PHY management */
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 4
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define CONFIG_ETHPRIME "TSEC0"
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
-#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
-#if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#if 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-#else
- #define CONFIG_SYS_FCC_PSMR 0
-#endif
- #define FETH2_RST 0x01
-#elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
-
-/* MDIO is done through the TSEC0 control.
-*/
-#define CONFIG_MII /* MII PHY management */
-#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
-
-#endif
-
-/* Environment - default config is in flash, see below */
-#if 0 /* in EEPROM */
-# define CONFIG_ENV_IS_IN_EEPROM 1
-# define CONFIG_ENV_OFFSET 0
-# define CONFIG_ENV_SIZE 2048
-#else /* in flash */
-# define CONFIG_ENV_IS_IN_FLASH 1
-# ifdef CONFIG_STXSSA_4M
-# define CONFIG_ENV_SECT_SIZE 0x20000
-# else /* default configuration - 64 MiB flash */
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# endif
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-# define CONFIG_ENV_SIZE 0x4000
-# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_TIMESTAMP /* Print image info with ts */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-#if !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_CMD_ELF
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-/*
- * Environment in EEPROM is compatible with different flash sector sizes,
- * but only little space is available, so we use a very simple setup.
- * With environment in flash, we use a more powerful default configuration.
- */
-#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
-
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
-#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
-#define CONFIG_SERVERIP 192.168.85.1
-#define CONFIG_IPADDR 192.168.85.60
-#define CONFIG_GATEWAYIP 192.168.85.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME STX_SSA
-#define CONFIG_ROOTPATH "/gppproot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x1000000
-
-#else /* ENV IS IN FLASH -- use a full-blown envionment */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=gp3ssa\0" \
- "bootfile=/tftpboot/gp3ssa/uImage\0" \
- "loadaddr=400000\0" \
- "netdev=eth0\0" \
- "consdev=ttyS1\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "addcons=setenv bootargs $bootargs " \
- "console=$consdev,$baudrate\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp $loadaddr $bootfile;" \
- "run nfsargs addip addcons;bootm\0" \
- "rootpath=/opt/eldk/ppc_85xx\0" \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC200000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [U-Boot, v2, 9/9] powerpc: mpc85xx: remove stxgp3, stxssa support
2015-09-02 1:40 ` [U-Boot] [PATCH v2 9/9] powerpc: mpc85xx: remove stxgp3, stxssa support Masahiro Yamada
@ 2015-09-02 21:59 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-09-02 21:59 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 10:40:30AM +0900, Masahiro Yamada wrote:
> These have not been converted to Generic Board, so should be removed.
> (See doc/README.generic-board for details.)
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Dan Malek <dan@embeddedalley.com>
Applied to u-boot/master, thanks!
--
Tom
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