From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel
Date: Thu, 3 Sep 2015 11:37:43 +0200 [thread overview]
Message-ID: <201509031137.43643.marex@denx.de> (raw)
In-Reply-To: <55E7DAE0.6030709@samsung.com>
On Thursday, September 03, 2015 at 07:30:08 AM, Jaehoon Chung wrote:
> Hi,
Hi,
> On 09/03/2015 09:27 AM, Chin Liang See wrote:
> > On Wed, 2015-09-02 at 12:32 +0200, marex at denx.de wrote:
> [snip]
thanks
> >>>>> Would want to hear more from Jaehoon as Exynos and SOCFPGA are the
> >>>>> one setting up these values.
> >>>>
> >>>> Since this approach is not based on dwmmc TRM, it's based on SOCFPGA
> >>>> SoC, i think that it doesn't need to include into dwmmc core.
> >>>> If need to located into dwmmc core, this code needs to modify more.
> >>>>
> >>>> As drvsel and clksmpl are used at Exynos and SoCFPGA, it's not core
> >>>> feature. Other SoC can't be used them. we don't know.
> >>>
> >>> Plus the way that this function is implemented, it is very specific to
> >>> SoCFGA, as the tables and rows are representing 45 degree increments
> >>> for the drvsel and smplsel value. Other platforms can have either more
> >>> or less granularity in the drvsel and smplsel values.
> >>
> >> How is this SMPLSEL and DRVSEL implemented on Exynos ?
>
> Exynos is using CLKSEL register in dw-mmc controller.
> It's exynos specific register in dwmmc controller. It's also represented 45
> degree increment. SELCK_DRV is bit[18:16] or more. SELCLK_SAMPLE is
> bit[2:0] or more. There are other bits relevant to tuning clock. '_more_'
> means that it can be changed bandwidth.
>
> Anyway, I think there is no right method about finding the best smplclk and
> drvsel. If this is generic method, i will pick this. But i don't think so,
> and there is no benefit for exynos.
>
> smplclk and drvsel value need to process the tuning sequence.
> There is no tuning case at bootloader, since it's not implemented about
> HS200 or upper mode.
>
> Clksel an drvsel value are passed by device tree.
In that case, maybe SoCFPGA should also pick those values from DT ? It would
keep the code simple and in case there is a problematic board, it could use
u-boot application to perform the tuning.
Best regards,
Marek Vasut
next prev parent reply other threads:[~2015-09-03 9:37 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-19 5:54 [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel Chin Liang See
2015-08-19 7:26 ` Pavel Machek
2015-08-19 7:34 ` Marek Vasut
2015-08-19 8:30 ` Chin Liang See
2015-08-19 23:23 ` Marek Vasut
2015-08-19 8:33 ` Chin Liang See
2015-08-19 7:40 ` Marek Vasut
2015-08-19 8:21 ` Chin Liang See
2015-08-19 19:36 ` Marek Vasut
2015-08-20 5:28 ` Chin Liang See
2015-08-20 5:32 ` Marek Vasut
2015-08-20 21:55 ` Dinh Nguyen
2015-08-20 21:59 ` Marek Vasut
2015-08-21 0:33 ` Dinh Nguyen
2015-08-21 0:42 ` Marek Vasut
2015-08-21 20:52 ` Simon Glass
2015-08-24 15:04 ` Chin Liang See
2015-08-25 2:36 ` Jaehoon Chung
2015-08-25 3:08 ` Chin Liang See
2015-08-26 5:29 ` Jaehoon Chung
2015-08-26 5:47 ` Chin Liang See
2015-08-26 6:14 ` Jaehoon Chung
2015-08-26 6:54 ` Chin Liang See
2015-09-01 8:54 ` Chin Liang See
2015-09-01 9:01 ` Marek Vasut
2015-09-01 9:10 ` Chin Liang See
2015-09-01 10:12 ` Jaehoon Chung
2015-09-01 14:53 ` Dinh Nguyen
2015-09-02 10:32 ` Marek Vasut
2015-09-03 0:27 ` Chin Liang See
2015-09-03 5:30 ` Jaehoon Chung
2015-09-03 9:37 ` Marek Vasut [this message]
2015-09-03 14:06 ` Chin Liang See
2015-09-03 14:25 ` Marek Vasut
2015-09-04 10:41 ` Pavel Machek
2015-09-07 8:33 ` Jaehoon Chung
2015-09-08 1:32 ` Chin Liang See
2015-09-08 10:56 ` Marek Vasut
[not found] ` <0016CF5815A1B142902817051AF62EB305FDF5BA@PG-ITEXCH01.altera.priv.altera.com>
2015-10-07 2:54 ` Chin Liang See
2015-10-12 14:44 ` Marek Vasut
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