From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Thu, 3 Sep 2015 16:25:08 +0200
Subject: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for
	drvsel and smpsel
In-Reply-To: <1441289172.1889.2.camel@clsee-VirtualBox>
References: <1439963690-2523-1-git-send-email-clsee@altera.com>
 <201509031137.43643.marex@denx.de> <1441289172.1889.2.camel@clsee-VirtualBox>
Message-ID: <201509031625.08677.marex@denx.de>
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To: u-boot@lists.denx.de

On Thursday, September 03, 2015 at 04:06:12 PM, Chin Liang See wrote:
> Hi,
> 
> On Thu, 2015-09-03 at 11:37 +0200, marex at denx.de wrote:
> > On Thursday, September 03, 2015 at 07:30:08 AM, Jaehoon Chung wrote:
> > > Hi,
> > 
> > Hi,
> > 
> > > On 09/03/2015 09:27 AM, Chin Liang See wrote:
> > > > On Wed, 2015-09-02 at 12:32 +0200, marex at denx.de wrote:
> > > [snip]
> > 
> > thanks
> > 
> > > >>>>> Would want to hear more from Jaehoon as Exynos and SOCFPGA are
> > > >>>>> the one setting up these values.
> > > >>>> 
> > > >>>> Since this approach is not based on dwmmc TRM, it's based on
> > > >>>> SOCFPGA SoC, i think that it doesn't need to include into dwmmc
> > > >>>> core. If need to located into dwmmc core, this code needs to
> > > >>>> modify more.
> > > >>>> 
> > > >>>> As drvsel and clksmpl are used at Exynos and SoCFPGA, it's not
> > > >>>> core feature. Other SoC can't be used them. we don't know.
> > > >>> 
> > > >>> Plus the way that this function is implemented, it is very specific
> > > >>> to SoCFGA, as the tables and rows are representing 45 degree
> > > >>> increments for the drvsel and smplsel value. Other platforms can
> > > >>> have either more or less granularity in the drvsel and smplsel
> > > >>> values.
> > > >> 
> > > >> How is this SMPLSEL and DRVSEL implemented on Exynos ?
> > > 
> > > Exynos is using CLKSEL register in dw-mmc controller.
> > > It's exynos specific register in dwmmc controller. It's also
> > > represented 45 degree increment. SELCK_DRV is bit[18:16] or more.
> > > SELCLK_SAMPLE is bit[2:0] or more. There are other bits relevant to
> > > tuning clock. '_more_' means that it can be changed bandwidth.
> > > 
> > > Anyway, I think there is no right method about finding the best smplclk
> > > and drvsel. If this is generic method, i will pick this. But i don't
> > > think so, and there is no benefit for exynos.
> > > 
> > > smplclk and drvsel value need to process the tuning sequence.
> > > There is no tuning case at bootloader, since it's not implemented about
> > > HS200 or upper mode.
> > > 
> > > Clksel an drvsel value are passed by device tree.
> > 
> > In that case, maybe SoCFPGA should also pick those values from DT ? It
> > would keep the code simple and in case there is a problematic board, it
> > could use u-boot application to perform the tuning.
> 
> I prefer not to do that as it narrows the supported use case for the
> driver.

How so? It keeps the driver code clean and this code you're adding seems
like a special-purpose stuff which needs to be done once for particular
board, no ?

Best regards,
Marek Vasut