From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pavel Machek Date: Fri, 4 Sep 2015 12:41:41 +0200 Subject: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel In-Reply-To: <201509031625.08677.marex@denx.de> References: <1439963690-2523-1-git-send-email-clsee@altera.com> <201509031137.43643.marex@denx.de> <1441289172.1889.2.camel@clsee-VirtualBox> <201509031625.08677.marex@denx.de> Message-ID: <20150904104141.GC31035@amd> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi! > > > > >> How is this SMPLSEL and DRVSEL implemented on Exynos ? > > > > > > > > Exynos is using CLKSEL register in dw-mmc controller. > > > > It's exynos specific register in dwmmc controller. It's also > > > > represented 45 degree increment. SELCK_DRV is bit[18:16] or more. > > > > SELCLK_SAMPLE is bit[2:0] or more. There are other bits relevant to > > > > tuning clock. '_more_' means that it can be changed bandwidth. > > > > > > > > Anyway, I think there is no right method about finding the best smplclk > > > > and drvsel. If this is generic method, i will pick this. But i don't > > > > think so, and there is no benefit for exynos. > > > > > > > > smplclk and drvsel value need to process the tuning sequence. > > > > There is no tuning case at bootloader, since it's not implemented about > > > > HS200 or upper mode. > > > > > > > > Clksel an drvsel value are passed by device tree. > > > > > > In that case, maybe SoCFPGA should also pick those values from DT ? It > > > would keep the code simple and in case there is a problematic board, it > > > could use u-boot application to perform the tuning. > > > > I prefer not to do that as it narrows the supported use case for the > > driver. > > How so? It keeps the driver code clean and this code you're adding seems > like a special-purpose stuff which needs to be done once for particular > board, no ? Well... stuff that can be automatically detected is not supposed to be in the device tree. clksel and drvsel can be calibrated, so I see some arguments why we should calibrate them, and not hardcode them in the device tree. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html