[U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

Stephen Warren
2015-09-10T03:37:34Z

On 09/08/2015 02:38 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Enabling a PLL while IDDQ is high. The Linux kernel checks for this

Is there some word missing in/at-the-end-of that first sentence? It
doesn't seem complete.

> condition and warns about it verbosely, so while this seems to work
> fine, fix it up according to the programming guidelines provided in
> the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
> Sequence").