From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Sat, 12 Sep 2015 09:04:06 +0200
Subject: [U-Boot] [PATCH] arm: armv8 correct value passed to
	__asm_dcache_all
In-Reply-To: <1438854853-8126-1-git-send-email-Peng.Fan@freescale.com>
References: <1438854853-8126-1-git-send-email-Peng.Fan@freescale.com>
Message-ID: <20150912090406.61817961@lilith>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hello Peng,

On Thu, 6 Aug 2015 17:54:13 +0800, Peng Fan <Peng.Fan@freescale.com> wrote:
> From source code comments:
> "x0: 0 flush & invalidate, 1 invalidate only"
> 
> Current value 0xffff can make invalidate work, since we only judge whether
> input value is 0 or not, see following code:
> "
>     tbz     w1, #0, 1f
>     dc      isw, x9
>     b       2f
> 1:  dc      cisw, x9      /* clean & invalidate by set/way */
> 2:  subs    x6, x6, #1    /* decrement the way */
> "
> 
> Later we may add "2 clean only" support. So following the comments,
> correct value from 0xffff to 1.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Cc: York Sun <yorksun@freescale.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> 
> Note:
> The patch was done when I was reading the source code.
> Since I do not have a board support armv8, I do not test this patch
> on real board.
> 
>  arch/arm/cpu/armv8/cache.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
> index d846236..ab8c089 100644
> --- a/arch/arm/cpu/armv8/cache.S
> +++ b/arch/arm/cpu/armv8/cache.S
> @@ -112,7 +112,7 @@ ENDPROC(__asm_flush_dcache_all)
>  
>  ENTRY(__asm_invalidate_dcache_all)
>  	mov	x16, lr
> -	mov	x0, #0xffff
> +	mov	x0, #0x1
>  	bl	__asm_dcache_all
>  	mov	lr, x16
>  	ret
> -- 
> 1.8.4
> 
> 

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.