[U-Boot] [PATCH] arm: socfpga: Fix cache configuration

[Pavel Machek <pavel@denx.de>]

On Thu 2015-09-17 17:30:29, Stefan Roese wrote:
> By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache
> policy is selected. This leads to much better performance on the SoCFPGA.
> A quick network test shows this:
> 
> Without this patch:
> => tftp 100000 big-40mb
> Speed: 1000, full duplex
> Using dwmac.ff702000 device
> TFTP from server 192.168.1.54; our IP address is 192.168.1.252
> Filename 'big-40mb'.
> Load address: 0x100000
> Loading: #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          ##########################
>          2.5 MiB/s
> 
> With this patch:
> => tftp 100000 big-40mb
> Speed: 1000, full duplex
> Using dwmac.ff702000 device
> TFTP from server 192.168.1.54; our IP address is 192.168.1.252
> Filename 'big-40mb'.
> Load address: 0x100000
> Loading: #################################################################
>          #################################################################
>          #################################################################
>          #################################################################
>          ##########################
>          7.6 MiB/s
> 
> A performance improvement of factor ~3.

Ok, so you turn on write-back cache and it is faster.

Now... do you have an explanation why this is safe to do? Are there
cache flushes that need to be added to the code now that we turned on
write-back?

Best regards,
									Pavel

> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 38ae763..a2811ba 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -73,7 +73,6 @@
>  /*
>   * Cache
>   */
> -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
>  #define CONFIG_SYS_CACHELINE_SIZE 32
>  #define CONFIG_SYS_L2_PL310
>  #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

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