[U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data

Marek Vasut
2015-10-08T21:39:18Z

On Tuesday, October 06, 2015 at 10:20:00 AM, Thomas Chou wrote:
> Convert cache flush to use dm cpu data. The cacheflush.c of
> Linux nios2 arch is copied to arch/nios2/lib/cache.c to replace
> the cache.S. The cache related functions in cpu.c is moved
> to cache.c. Both flush_dcache() and flush_icache() are
> replaced and removed. The flush_dcache_all() now flush icache
> too, which is

... confusing as hell :-(

> the same as what is done in Linux nios2 arch.
>
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
> arch/nios2/cpu/cpu.c | 15 --------
> arch/nios2/include/asm/cache.h | 13 ++-----
> arch/nios2/lib/bootm.c | 6 +--
> arch/nios2/lib/cache.S | 68 ----------------------------------
> arch/nios2/lib/cache.c | 84
> ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 88
> insertions(+), 98 deletions(-)
> delete mode 100644 arch/nios2/lib/cache.S
> create mode 100644 arch/nios2/lib/cache.c
>
> diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
> index 5403c0d..8607c95 100644
> --- a/arch/nios2/cpu/cpu.c
> +++ b/arch/nios2/cpu/cpu.c
> @@ -29,21 +29,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char
> * const argv[]) return 0;
> }
>
> -int dcache_status(void)
> -{
> - return 1;
> -}
> -
> -void dcache_enable(void)
> -{
> - flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
> -}
> -
> -void dcache_disable(void)
> -{
> - flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
> -}
> -
> /*
> * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
> * exception address. Define CONFIG_ROM_STUBS to prevent
> diff --git a/arch/nios2/include/asm/cache.h
> b/arch/nios2/include/asm/cache.h index 9b87c9f..dde43cd 100644
> --- a/arch/nios2/include/asm/cache.h
> +++ b/arch/nios2/include/asm/cache.h
> @@ -8,18 +8,11 @@
> #ifndef __ASM_NIOS2_CACHE_H_
> #define __ASM_NIOS2_CACHE_H_
>
> -extern void flush_dcache (unsigned long start, unsigned long size);
> -extern void flush_icache (unsigned long start, unsigned long size);
> -
> /*
> - * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16,
> and 32 - * bytes. If the board configuration has not specified one we
> default to the - * largest of these values for alignment of DMA buffers.
> + * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
> + * 16, and 32 bytes. We default to the largest of these values for
> + * alignment of DMA buffers.
> */
> -#ifdef CONFIG_SYS_CACHELINE_SIZE
> -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
> -#else
> #define ARCH_DMA_MINALIGN 32
> -#endif
>
> #endif /* __ASM_NIOS2_CACHE_H_ */
> diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c
> index c730a3f..4e5c269 100644
> --- a/arch/nios2/lib/bootm.c
> +++ b/arch/nios2/lib/bootm.c
> @@ -6,9 +6,6 @@
> */
>
> #include <common.h>
> -#include <command.h>
> -#include <asm/byteorder.h>
> -#include <asm/cache.h>
>
> #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
>
> @@ -40,8 +37,7 @@ int do_bootm_linux(int flag, int argc, char * const
> argv[], bootm_headers_t *ima
>
> /* flushes data and instruction caches before calling the kernel */
> disable_interrupts();
> - flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
> - flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
> + flush_dcache_all();
>
> debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
> debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
> diff --git a/arch/nios2/lib/cache.S b/arch/nios2/lib/cache.S
> deleted file mode 100644
> index 683f005..0000000
> --- a/arch/nios2/lib/cache.S
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -/*
> - * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
> - * Scott McNutt <smcnutt@psyent.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <config.h>
> -
> - .text
> -
> - .global flush_dcache
> -
> -flush_dcache:
> - add r5, r5, r4
> - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
> - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
> -0: flushd 0(r4)
> - add r4, r4, r8
> - bltu r4, r5, 0b
> - ret
> -
> -
> - .global flush_icache
> -
> -flush_icache:
> - add r5, r5, r4
> - movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
> - ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
> -1: flushi r4
> - add r4, r4, r8
> - bltu r4, r5, 1b
> - ret
> -
> - .global flush_dcache_range
> -
> -flush_dcache_range:
> - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
> - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
> -0: flushd 0(r4)
> - add r4, r4, r8
> - bltu r4, r5, 0b
> - ret
> -
> - .global flush_cache
> -
> -flush_cache:
> - add r5, r5, r4
> - mov r9, r4
> - mov r10, r5
> -
> - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
> - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
> -0: flushd 0(r4)
> - add r4, r4, r8
> - bltu r4, r5, 0b
> -
> - mov r4, r9
> - mov r5, r10
> - movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
> - ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
> -1: flushi r4
> - add r4, r4, r8
> - bltu r4, r5, 1b
> -
> - sync
> - flushp
> - ret
> diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c
> new file mode 100644
> index 0000000..6f26d8d
> --- /dev/null
> +++ b/arch/nios2/lib/cache.c
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
> + * Copyright (C) 2009, Wind River Systems Inc
> + * Implemented by fredrik.markstrom at gmail.com and ivarholmqvist at gmail.com
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/cache.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void __flush_dcache_all(unsigned long start, unsigned long end)
> +{
> + unsigned long addr;
> +
> + start &= ~(gd->arch.dcache_line_size - 1);

I'd suggest to use GENMASK() here, but I don't think we picked this from Linux
just yet.

> + end += (gd->arch.dcache_line_size - 1);
> + end &= ~(gd->arch.dcache_line_size - 1);

Is this an attempt at poor-mans' rounding ? I think you want to implment
something like arch/arm/cpu/arm926ejs/cache.c check_cache_range() and NOT
do any rounding here. The reason for that is that if you do rounding, you
might accidentally corrupt a piece of memory which was just delivered via
DMA before you did the flush.

> + if (end > start + gd->arch.dcache_size)
> + end = start + gd->arch.dcache_size;
> +
> + for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
> + __asm__ __volatile__ (" flushd 0(%0)\n"
> + : /* Outputs */
> + : /* Inputs */ "r"(addr)
> + /* : No clobber */);
> + }
> +}
> +
> +static void __flush_icache(unsigned long start, unsigned long end)
> +{
> + unsigned long addr;
> +
> + start &= ~(gd->arch.icache_line_size - 1);
> + end += (gd->arch.icache_line_size - 1);
> + end &= ~(gd->arch.icache_line_size - 1);
> +
> + if (end > start + gd->arch.icache_size)
> + end = start + gd->arch.icache_size;
> +
> + for (addr = start; addr < end; addr += gd->arch.icache_line_size) {
> + __asm__ __volatile__ (" flushi %0\n"
> + : /* Outputs */
> + : /* Inputs */ "r"(addr)
> + /* : No clobber */);
> + }
> + __asm__ __volatile(" flushp\n");
> +}
> +
> +void flush_dcache_all(void)
> +{
> + __flush_dcache_all(0, gd->arch.dcache_size);
> + __flush_icache(0, gd->arch.icache_size);
> +}
> +
> +void flush_dcache_range(unsigned long start, unsigned long end)
> +{
> + __flush_dcache_all(start, end);
> +}
> +
> +void flush_cache(unsigned long start, unsigned long size)
> +{
> + __flush_dcache_all(start, start + size);
> + __flush_icache(start, start + size);
> +}
> +
> +/* nios2 data cache is always enabled */
> +int dcache_status(void)
> +{
> + return 1;
> +}
> +
> +void dcache_enable(void)
> +{
> + flush_dcache_all();
> +}
> +
> +void dcache_disable(void)
> +{
> + flush_dcache_all();
> +}