* [U-Boot] [PATCH 2/3] armv8/mmu: Set bits marked RES1 in TCR
2015-08-20 9:52 [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming Thierry Reding
@ 2015-08-20 9:52 ` Thierry Reding
2015-08-20 9:52 ` [U-Boot] [PATCH 3/3] armv8/gic: Fix GIC v2 initialization Thierry Reding
2015-10-15 12:52 ` [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming Albert ARIBAUD
2 siblings, 0 replies; 4+ messages in thread
From: Thierry Reding @ 2015-08-20 9:52 UTC (permalink / raw)
To: u-boot
From: Thierry Reding <treding@nvidia.com>
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/cpu/armv8/cache_v8.c | 6 +++---
arch/arm/include/asm/armv8/mmu.h | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 835f6a6525ea..2ee2e229afd9 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -50,15 +50,15 @@ static void mmu_setup(void)
el = current_el();
if (el == 1) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL1_IPS_BITS,
+ TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
MEMORY_ATTRIBUTES);
} else if (el == 2) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL2_IPS_BITS,
+ TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
MEMORY_ATTRIBUTES);
} else {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL3_IPS_BITS,
+ TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
MEMORY_ATTRIBUTES);
}
/* enable the mmu */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 6d42f5533a74..8e577b34e4ba 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -109,6 +109,10 @@
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
+#define TCR_EL1_RSVD (1 << 31)
+#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
+#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
+
#ifndef __ASSEMBLY__
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type);
--
2.4.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 3/3] armv8/gic: Fix GIC v2 initialization
2015-08-20 9:52 [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming Thierry Reding
2015-08-20 9:52 ` [U-Boot] [PATCH 2/3] armv8/mmu: Set bits marked RES1 in TCR Thierry Reding
@ 2015-08-20 9:52 ` Thierry Reding
2015-10-15 12:52 ` [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming Albert ARIBAUD
2 siblings, 0 replies; 4+ messages in thread
From: Thierry Reding @ 2015-08-20 9:52 UTC (permalink / raw)
To: u-boot
From: Thierry Reding <treding@nvidia.com>
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/lib/gic_64.S | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index a3e18f7713e5..62d0022408bc 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -46,11 +46,19 @@ ENTRY(gic_init_secure)
ldr w9, [x0, GICD_TYPER]
and w10, w9, #0x1f /* ITLinesNumber */
cbz w10, 1f /* No SPIs */
- add x11, x0, (GICD_IGROUPRn + 4)
+ add x11, x0, GICD_IGROUPRn
mov w9, #~0 /* Config SPIs as Grp1 */
+ str w9, [x11], #0x4
0: str w9, [x11], #0x4
sub w10, w10, #0x1
cbnz w10, 0b
+
+ ldr x1, =GICC_BASE /* GICC_CTLR */
+ mov w0, #3 /* EnableGrp0 | EnableGrp1 */
+ str w0, [x1]
+
+ mov w0, #1 << 7 /* allow NS access to GICC_PMR */
+ str w0, [x1, #4] /* GICC_PMR */
#endif
1:
ret
--
2.4.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming
2015-08-20 9:52 [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming Thierry Reding
2015-08-20 9:52 ` [U-Boot] [PATCH 2/3] armv8/mmu: Set bits marked RES1 in TCR Thierry Reding
2015-08-20 9:52 ` [U-Boot] [PATCH 3/3] armv8/gic: Fix GIC v2 initialization Thierry Reding
@ 2015-10-15 12:52 ` Albert ARIBAUD
2 siblings, 0 replies; 4+ messages in thread
From: Albert ARIBAUD @ 2015-10-15 12:52 UTC (permalink / raw)
To: u-boot
Hello Thierry,
On Thu, 20 Aug 2015 11:52:13 +0200, Thierry Reding
<thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Use the inner shareable attribute for memory, which makes more sense
> considering that this code is called when caches are being enabled.
>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
Series applied to u-boot-arm/master as a bugfix.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 4+ messages in thread