From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Mon, 19 Oct 2015 07:52:25 +0200
Subject: [U-Boot] [PATCH v4] nios2: convert dma_alloc_coherent to use
 malloc_cache_aligned
In-Reply-To: <561BADA7.1050008@wytron.com.tw>
References: <1444013823-11909-1-git-send-email-thomas@wytron.com.tw>
 <1444627783-15105-1-git-send-email-thomas@wytron.com.tw>
 <201510121232.56484.marex@denx.de> <561BADA7.1050008@wytron.com.tw>
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Hello Thomas,

On Mon, 12 Oct 2015 20:55:03 +0800, Thomas Chou <thomas@wytron.com.tw>
wrote:
> Hi Marek,
> 
> On 10/12/2015 06:32 PM, Marek Vasut wrote:
> > Wouldn't invalidate_dcache_range() be enough here ? You don't care about the
> > data in the newly allocated area at this point I guess -- either you fill them
> > in and then flush, for DMA from CPU to device OR you receive data from device
> > to CPU and then you invalidate this buffer again.
> 
> No. We cannot use invalidate cache here. This is related to cache design 
> of nios2, kind of direct mapped cache.

Not sure I'm getting this, so for my own education: what prevents from
invalidating the cache, or IOW, what would happen if it was invalidated
at this point rather than flushed?

> Best regards,
> Thomas

Amicalement,
-- 
Albert.