From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK
Date: Fri, 23 Oct 2015 20:18:56 +0200 [thread overview]
Message-ID: <201510232018.56541.marex@denx.de> (raw)
In-Reply-To: <1445547024-7774-19-git-send-email-jteki@openedev.com>
On Thursday, October 22, 2015 at 10:50:18 PM, Jagan Teki wrote:
> Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb
>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
> drivers/spi/cadence_qspi_apb.c | 48
> +++++++++++++++++++++--------------------- 1 file changed, 24
> insertions(+), 24 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index 7786dd6..31e14ee 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -44,7 +44,7 @@
> #define CQSPI_INST_TYPE_QUAD (2)
>
> #define CQSPI_STIG_DATA_LEN_MAX (8)
> -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK GENMASK(19, 0)
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE (8)
> #define CQSPI_DUMMY_BYTES_MAX (4)
> @@ -65,8 +65,8 @@
> #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
> #define CQSPI_REG_CONFIG_BAUD_LSB 19
> #define CQSPI_REG_CONFIG_IDLE_LSB 31
> -#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
> -#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
> +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK GENMASK(3, 0)
> +#define CQSPI_REG_CONFIG_BAUD_MASK GENMASK(3, 0)
>
> #define CQSPI_REG_RD_INSTR 0x04
> #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
> @@ -75,10 +75,10 @@
> #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
> #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
> #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
> -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
> -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
> -#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
> -#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
> +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK GENMASK(1, 0)
> +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK GENMASK(1, 0)
> +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK GENMASK(1, 0)
> +#define CQSPI_REG_RD_INSTR_DUMMY_MASK GENMASK(4, 0)
>
> #define CQSPI_REG_WR_INSTR 0x08
> #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
> @@ -88,23 +88,23 @@
> #define CQSPI_REG_DELAY_TCHSH_LSB 8
> #define CQSPI_REG_DELAY_TSD2D_LSB 16
> #define CQSPI_REG_DELAY_TSHSL_LSB 24
> -#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
> -#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
> -#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
> -#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
> +#define CQSPI_REG_DELAY_TSLCH_MASK GENMASK(7, 0)
> +#define CQSPI_REG_DELAY_TCHSH_MASK GENMASK(7, 0)
> +#define CQSPI_REG_DELAY_TSD2D_MASK GENMASK(7, 0)
> +#define CQSPI_REG_DELAY_TSHSL_MASK GENMASK(7, 0)
>
> #define CQSPI_READLCAPTURE 0x10
> #define CQSPI_READLCAPTURE_BYPASS_LSB 0
> #define CQSPI_READLCAPTURE_DELAY_LSB 1
> -#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
> +#define CQSPI_READLCAPTURE_DELAY_MASK GENMASK(3, 0)
>
> #define CQSPI_REG_SIZE 0x14
> #define CQSPI_REG_SIZE_ADDRESS_LSB 0
> #define CQSPI_REG_SIZE_PAGE_LSB 4
> #define CQSPI_REG_SIZE_BLOCK_LSB 16
> -#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
> -#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
> -#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
> +#define CQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0)
> +#define CQSPI_REG_SIZE_PAGE_MASK GENMASK(11, 0)
> +#define CQSPI_REG_SIZE_BLOCK_MASK GENMASK(5, 0)
>
> #define CQSPI_REG_SRAMPARTITION 0x18
> #define CQSPI_REG_INDIRECTTRIGGER 0x1C
> @@ -115,8 +115,8 @@
> #define CQSPI_REG_SDRAMLEVEL 0x2C
> #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
> #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
> -#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
> -#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
> +#define CQSPI_REG_SDRAMLEVEL_RD_MASK GENMASK(15, 0)
> +#define CQSPI_REG_SDRAMLEVEL_WR_MASK GENMASK(15, 0)
>
> #define CQSPI_REG_IRQSTATUS 0x40
> #define CQSPI_REG_IRQMASK 0x44
> @@ -142,11 +142,11 @@
> #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
> #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
> #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
> -#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
> -#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
> -#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
> -#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
> -#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
> +#define CQSPI_REG_CMDCTRL_DUMMY_MASK GENMASK(4, 0)
> +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK GENMASK(2, 0)
> +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK GENMASK(1, 0)
> +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK GENMASK(2, 0)
> +#define CQSPI_REG_CMDCTRL_OPCODE_MASK GENMASK(7, 0)
Sorry, this just decreased the clarify of the code, so
NAK
next prev parent reply other threads:[~2015-10-23 18:18 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-22 20:50 [U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 01/24] spi: zynq_[q]spi: Use BIT macro Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 02/24] spi: zynq_[q]spi: Use GENMASK macro Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 03/24] spi: altera_spi: Use BIT macro Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 04/24] spi: atmel_spi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 05/24] spi: bfin_spi6xx: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-23 17:11 ` Vikas MANOCHA
2015-10-22 20:50 ` [U-Boot] [PATCH v4 07/24] spi: designware_spi: " Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 08/24] spi: exynos_spi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-24 3:26 ` Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 09/24] spi: fsl: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 10/24] spi: ich: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 11/24] spi: mpc8xxx_spi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 12/24] spi: omap3_spi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 13/24] spi: sh_qspi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 14/24] spi: tegra: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 15/24] spi: ti_qspi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 16/24] spi: xilinx_spi: " Jagan Teki
2015-10-22 21:24 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 17/24] spi: atmel_spi: Use GENMASK Jagan Teki
2015-10-22 21:25 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: " Jagan Teki
2015-10-22 21:10 ` Fabio Estevam
2015-10-22 21:25 ` Tom Rini
2015-10-23 17:17 ` Jagan Teki
2015-10-23 18:17 ` Marek Vasut
2015-10-23 18:39 ` Fabio Estevam
2015-10-23 20:03 ` Tom Rini
2015-10-23 17:11 ` Vikas MANOCHA
2015-10-23 18:18 ` Marek Vasut [this message]
2015-10-22 20:50 ` [U-Boot] [PATCH v4 19/24] spi: designware_spi: " Jagan Teki
2015-10-22 21:25 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 20/24] spi: fsl_qspi: " Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 21/24] spi: mxs_spi: " Jagan Teki
2015-10-22 21:08 ` Fabio Estevam
2015-10-22 21:15 ` Jagan Teki
2015-10-22 21:18 ` Fabio Estevam
2015-10-23 8:23 ` Jagan Teki
2015-10-22 21:30 ` Marek Vasut
2015-10-23 8:27 ` Jagan Teki
2015-10-22 21:25 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 22/24] spi: omap3_spi: " Jagan Teki
2015-10-22 21:25 ` Tom Rini
2015-10-22 20:50 ` [U-Boot] [PATCH v4 23/24] spi: tegra: " Jagan Teki
2015-10-22 20:50 ` [U-Boot] [PATCH v4 24/24] spi: xilinx_spi: " Jagan Teki
2015-10-22 21:25 ` [U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK Tom Rini
2015-10-23 17:10 ` Jagan Teki
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