From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peng Fan Date: Mon, 26 Oct 2015 11:24:50 +0800 Subject: [U-Boot] [PATCH V2 09/14] video: mxsfb: introduce lcdif_power_down In-Reply-To: <562648B6.2040905@denx.de> References: <1445341184-22272-1-git-send-email-Peng.Fan@freescale.com> <1445341184-22272-10-git-send-email-Peng.Fan@freescale.com> <562648B6.2040905@denx.de> Message-ID: <20151026032449.GF13617@shlinux2> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Stefano, On Tue, Oct 20, 2015 at 03:59:18PM +0200, Stefano Babic wrote: >Hi Peng, > >On 20/10/2015 13:39, Peng Fan wrote: >> Introudce a new function lcdif_power_down. >> >> 1. Waits for a VSYNC interrupt to guarantee the reset is done at the >> VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?) >> and helps the LCDIF work normally at the kernel stage. >> 2. Add power down function to stop lcdif. >> >> The reason to introduce lcdif_power_down is that we want lcdif to be in >> initial state when doing uboot reset or before kernel boot to make >> system stable, otherwise system may hang. >> > >The explanation is independent from the processor type. But checking in >the next patch, this code runs only for 6UL. Why not for the 6sx ? We met the issue on i.MX6UL EVK, but did not met issue on i.MX6SX SDB. So I add the check. After a thought, it should be open to CONFIG_VIDEO_MXS. To those which use LPDDR2 or LPDDR3, if LCDIF is enabled, lcdif_power_down is a must, since there is no reset pin as DDR3. No reset pin will make ddr not stable. Anyway lcdif_power_down do not hurts to those use DDR3. Will use #ifdef CONFIG_VIDEO_MXS lcdif_power_down(); #endif Regards, Peng. > > >> Signed-off-by: Peng Fan >> Cc: Stefano Babic >> Cc: Anatolij Gustschin >> --- >> >> V2: >> none >> >> arch/arm/include/asm/imx-common/sys_proto.h | 2 ++ >> drivers/video/mxsfb.c | 17 +++++++++++++++++ >> 2 files changed, 19 insertions(+) >> >> diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h >> index 5673fb4..386c2dc 100644 >> --- a/arch/arm/include/asm/imx-common/sys_proto.h >> +++ b/arch/arm/include/asm/imx-common/sys_proto.h >> @@ -47,6 +47,8 @@ int fecmxc_initialize(bd_t *bis); >> u32 get_ahb_clk(void); >> u32 get_periph_clk(void); >> >> +void lcdif_power_down(void); >> + >> int mxs_reset_block(struct mxs_register_32 *reg); >> int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); >> int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); >> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c >> index eed57d5..ddbb118 100644 >> --- a/drivers/video/mxsfb.c >> +++ b/drivers/video/mxsfb.c >> @@ -131,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel, >> writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); >> } >> >> +void lcdif_power_down(void) >> +{ >> + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; >> + int timeout = 1000000; >> + >> + writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg); >> + writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg); >> + writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr); >> + while (--timeout) { >> + if (readl(®s->hw_lcdif_ctrl1_reg) & >> + LCDIF_CTRL1_VSYNC_EDGE_IRQ) >> + break; >> + udelay(1); >> + } >> + mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg); >> +} >> + >> void *video_hw_init(void) >> { >> int bpp = -1; >> > >Best regards, >Stefano Babic > >-- >===================================================================== >DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de >===================================================================== --