From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Mon, 9 Nov 2015 01:10:45 +0100 Subject: [U-Boot] [PATCH] arm: socfpga: Fix cache configuration In-Reply-To: <1442503829-28882-1-git-send-email-sr@denx.de> References: <1442503829-28882-1-git-send-email-sr@denx.de> Message-ID: <201511090110.45996.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday, September 17, 2015 at 05:30:29 PM, Stefan Roese wrote: Hi! > By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache > policy is selected. This leads to much better performance on the SoCFPGA. > A quick network test shows this: > > Without this patch: > => tftp 100000 big-40mb > Speed: 1000, full duplex > Using dwmac.ff702000 device > TFTP from server 192.168.1.54; our IP address is 192.168.1.252 > Filename 'big-40mb'. > Load address: 0x100000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ########################## > 2.5 MiB/s > > With this patch: > => tftp 100000 big-40mb > Speed: 1000, full duplex > Using dwmac.ff702000 device > TFTP from server 192.168.1.54; our IP address is 192.168.1.252 > Filename 'big-40mb'. > Load address: 0x100000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ########################## > 7.6 MiB/s > > A performance improvement of factor ~3. > > Signed-off-by: Stefan Roese > Cc: Dinh Nguyen > Cc: Chin Liang See > Cc: Pavel Machek > Cc: Marek Vasut > --- > include/configs/socfpga_common.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h index 38ae763..a2811ba 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -73,7 +73,6 @@ > /* > * Cache > */ > -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC > #define CONFIG_SYS_CACHELINE_SIZE 32 > #define CONFIG_SYS_L2_PL310 > #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS I hate to say it, but I am running into issues with this patch :-( I use a standard USB stick here and with this patch, I am getting the following failure (with enabled and disabled cache): => usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... unable to get descriptor, error 0 usb_new_device: Cannot read configuration, skipping device 058f:6387 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => dcache off => usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found If I revert this patch, my USB stick works as well. I am also aware that Stefan mentions that without this patch, cache is not enabled at all. On the other hand, I cannot find any obviously faulty behavior in the dwc2 driver, it does flush_dcache_range()/invalidate_dcache_range() in the right places. Any ideas please ? Best regards, Marek Vasut