* [U-Boot] socfpga, spl, status
@ 2015-11-20 14:49 Jan Viktorin
2015-11-20 16:21 ` Marek Vasut
0 siblings, 1 reply; 5+ messages in thread
From: Jan Viktorin @ 2015-11-20 14:49 UTC (permalink / raw)
To: u-boot
Hello Marek and U-Boot community,
I am trying to build the U-Boot 2015.10 with SPL for the EBV SoCrates
board (Altera SoC FPGA, Cyclone V). It builds, however, I am unable to
boot. It does not print any output. I can boot the SoCrates board with
an older bootloader generated by the Altera tools.
I am able to build & run U-Boot for Altera SoC Development Kit (NOT
SoCKit), the SPL works however U-Boot freezes...
U-Boot 2015.10 (Nov 20 2015 - 15:43:36 +0100)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: SOCFPGA DWMMC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Autoboot in 3 seconds
[...frozen here...]
So, what is the status of the SPL for SoCFPGA in upstream? Does anybody
test all the claimed socfpga platforms?
Regards
Jan Viktorin
--
Jan Viktorin E-mail: Viktorin at RehiveTech.com
System Architect Web: www.RehiveTech.com
RehiveTech
Brno, Czech Republic
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] socfpga, spl, status 2015-11-20 14:49 [U-Boot] socfpga, spl, status Jan Viktorin @ 2015-11-20 16:21 ` Marek Vasut 2015-11-20 16:27 ` Marek Vasut 0 siblings, 1 reply; 5+ messages in thread From: Marek Vasut @ 2015-11-20 16:21 UTC (permalink / raw) To: u-boot On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote: > Hello Marek and U-Boot community, Hi, ahoj, > I am trying to build the U-Boot 2015.10 with SPL for the EBV SoCrates > board (Altera SoC FPGA, Cyclone V). It builds, however, I am unable to > boot. It does not print any output. I can boot the SoCrates board with > an older bootloader generated by the Altera tools. The SoCrates was always a bit of an orphan, but I'm submitting a patch to fix it now, since I have one. > I am able to build & run U-Boot for Altera SoC Development Kit (NOT > SoCKit), the SPL works however U-Boot freezes... > > U-Boot 2015.10 (Nov 20 2015 - 15:43:36 +0100) > > CPU: Altera SoCFPGA Platform > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > BOOT: SD/MMC Internal Transceiver (3.0V) > Watchdog enabled > I2C: ready > DRAM: 1 GiB > MMC: SOCFPGA DWMMC: 0 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Model: Altera SOCFPGA Cyclone V SoC Development Kit > Autoboot in 3 seconds > [...frozen here...] > > So, what is the status of the SPL for SoCFPGA in upstream? Does anybody > test all the claimed socfpga platforms? I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna look at the CV SoCDK issue ? I might be able to set it up later this weekend, but don't hold your breath, I am pretty overloaded. Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] socfpga, spl, status 2015-11-20 16:21 ` Marek Vasut @ 2015-11-20 16:27 ` Marek Vasut 2015-11-20 18:41 ` Jan Viktorin 0 siblings, 1 reply; 5+ messages in thread From: Marek Vasut @ 2015-11-20 16:27 UTC (permalink / raw) To: u-boot On Friday, November 20, 2015 at 05:21:08 PM, Marek Vasut wrote: > On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote: > > Hello Marek and U-Boot community, > > Hi, ahoj, > > > I am trying to build the U-Boot 2015.10 with SPL for the EBV SoCrates > > board (Altera SoC FPGA, Cyclone V). It builds, however, I am unable to > > boot. It does not print any output. I can boot the SoCrates board with > > an older bootloader generated by the Altera tools. > > The SoCrates was always a bit of an orphan, but I'm submitting a patch to > fix it now, since I have one. > > > I am able to build & run U-Boot for Altera SoC Development Kit (NOT > > SoCKit), the SPL works however U-Boot freezes... > > > > U-Boot 2015.10 (Nov 20 2015 - 15:43:36 +0100) > > > > CPU: Altera SoCFPGA Platform > > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > > BOOT: SD/MMC Internal Transceiver (3.0V) > > > > Watchdog enabled > > > > I2C: ready > > DRAM: 1 GiB > > MMC: SOCFPGA DWMMC: 0 > > *** Warning - bad CRC, using default environment > > > > In: serial > > Out: serial > > Err: serial > > Model: Altera SOCFPGA Cyclone V SoC Development Kit > > Autoboot in 3 seconds > > [...frozen here...] > > > > So, what is the status of the SPL for SoCFPGA in upstream? Does anybody > > test all the claimed socfpga platforms? > > I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna look > at the CV SoCDK issue ? I might be able to set it up later this weekend, > but don't hold your breath, I am pretty overloaded. Update, my SoCdk boots just fine: U-Boot SPL 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC U-Boot 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50 +0100) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: SOCFPGA DWMMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: No ethernet found. Hit any key to stop autoboot: 0 => Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] socfpga, spl, status 2015-11-20 16:27 ` Marek Vasut @ 2015-11-20 18:41 ` Jan Viktorin 2015-11-20 19:45 ` Marek Vasut 0 siblings, 1 reply; 5+ messages in thread From: Jan Viktorin @ 2015-11-20 18:41 UTC (permalink / raw) To: u-boot On Fri, 20 Nov 2015 17:27:02 +0100 Marek Vasut <marex@denx.de> wrote: > On Friday, November 20, 2015 at 05:21:08 PM, Marek Vasut wrote: > > On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote: > > > Hello Marek and U-Boot community, > > [snip] > > > So, what is the status of the SPL for SoCFPGA in upstream? Does anybody > > > test all the claimed socfpga platforms? > > > > I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna look > > at the CV SoCDK issue ? I might be able to set it up later this weekend, > > but don't hold your breath, I am pretty overloaded. > > Update, my SoCdk boots just fine: > > U-Boot SPL 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50) > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED > drivers/ddr/altera/sequencer.c: Calibration complete > Trying to boot from MMC > > > U-Boot 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50 +0100) > > CPU: Altera SoCFPGA Platform > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > BOOT: SD/MMC External Transceiver (1.8V) > Watchdog enabled > I2C: ready > DRAM: 1 GiB > MMC: SOCFPGA DWMMC: 0 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Model: Altera SOCFPGA Cyclone V SoC Development Kit > Net: No ethernet found. > Hit any key to stop autoboot: 0 > => > > Best regards, > Marek Vasut Hi, thanks for quick replies. I tried the SoCDK with 2016-rc1 and the default config socfpga_cyclone5_defconfig. The previous build has used some customization of the config (I tried to disable EMAC). I build by the Buildroot using the uclibc toolchain. Installed as $ sudo dd if=u-boot-spl-dtb.bin.crc of=/dev/sdc1 bs=64k seek=0 $ sudo dd if=u-boot-dtb.img of=/dev/sdc1 bs=64k seek=4 Freezed again: U-Boot SPL 2016.01-rc1 (Nov 20 2015 - 17:49:39) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete U-Boot 2016.01-rc1 (Nov 20 2015 - 17:49:39 +0100) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: SOCFPGA DWMMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: [...freezed...] Regards Jan Viktorin -- Jan Viktorin E-mail: Viktorin at RehiveTech.com System Architect Web: www.RehiveTech.com RehiveTech Brno, Czech Republic ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] socfpga, spl, status 2015-11-20 18:41 ` Jan Viktorin @ 2015-11-20 19:45 ` Marek Vasut 0 siblings, 0 replies; 5+ messages in thread From: Marek Vasut @ 2015-11-20 19:45 UTC (permalink / raw) To: u-boot On Friday, November 20, 2015 at 07:41:30 PM, Jan Viktorin wrote: > On Fri, 20 Nov 2015 17:27:02 +0100 > > Marek Vasut <marex@denx.de> wrote: > > On Friday, November 20, 2015 at 05:21:08 PM, Marek Vasut wrote: > > > On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote: > > > > Hello Marek and U-Boot community, > > > > > > [snip] > > > > > > > So, what is the status of the SPL for SoCFPGA in upstream? Does > > > > anybody test all the claimed socfpga platforms? > > > > > > I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna > > > look at the CV SoCDK issue ? I might be able to set it up later this > > > weekend, but don't hold your breath, I am pretty overloaded. > > > > Update, my SoCdk boots just fine: > > > > U-Boot SPL 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50) > > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration > > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED > > drivers/ddr/altera/sequencer.c: Calibration complete > > Trying to boot from MMC > > > > > > U-Boot 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50 +0100) > > > > CPU: Altera SoCFPGA Platform > > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > > BOOT: SD/MMC External Transceiver (1.8V) > > > > Watchdog enabled > > > > I2C: ready > > DRAM: 1 GiB > > MMC: SOCFPGA DWMMC: 0 > > *** Warning - bad CRC, using default environment > > > > In: serial > > Out: serial > > Err: serial > > Model: Altera SOCFPGA Cyclone V SoC Development Kit > > Net: No ethernet found. > > Hit any key to stop autoboot: 0 > > => > > > > Best regards, > > Marek Vasut > > Hi, thanks for quick replies. > > I tried the SoCDK with 2016-rc1 and the default config > socfpga_cyclone5_defconfig. The previous build has used some > customization of the config (I tried to disable EMAC). I build > by the Buildroot using the uclibc toolchain. Installed as > > $ sudo dd if=u-boot-spl-dtb.bin.crc of=/dev/sdc1 bs=64k seek=0 > $ sudo dd if=u-boot-dtb.img of=/dev/sdc1 bs=64k seek=4 Do the following, the u-boot-with-spl-dtb.sfp is automatically generated by the build in 2016.01rc, while you need to do make u-boot-with-spl-dtb.sfp with 2015.10. This is actually important: $ sudo dd if=u-boot-with-spl-dtb.sfp of=/dev/sdc btw which version of gcc does your toolchain use ? It might be a compiler bug, I've seen those more than once. > Freezed again: > > U-Boot SPL 2016.01-rc1 (Nov 20 2015 - 17:49:39) > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED > drivers/ddr/altera/sequencer.c: Calibration complete > > > U-Boot 2016.01-rc1 (Nov 20 2015 - 17:49:39 +0100) > > CPU: Altera SoCFPGA Platform > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > BOOT: SD/MMC Internal Transceiver (3.0V) > Watchdog enabled > I2C: ready > DRAM: 1 GiB > MMC: SOCFPGA DWMMC: 0 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Model: Altera SOCFPGA Cyclone V SoC Development Kit > Net: > [...freezed...] > > Regards > Jan Viktorin Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-11-20 19:45 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-11-20 14:49 [U-Boot] socfpga, spl, status Jan Viktorin 2015-11-20 16:21 ` Marek Vasut 2015-11-20 16:27 ` Marek Vasut 2015-11-20 18:41 ` Jan Viktorin 2015-11-20 19:45 ` Marek Vasut
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox