From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 20 Nov 2015 20:45:08 +0100
Subject: [U-Boot] socfpga, spl, status
In-Reply-To: <20151120194130.21cf408c@pcviktorin.fit.vutbr.cz>
References: <20151120154946.19096238@pcviktorin.fit.vutbr.cz>
 <201511201727.02361.marex@denx.de>
 <20151120194130.21cf408c@pcviktorin.fit.vutbr.cz>
Message-ID: <201511202045.08918.marex@denx.de>
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To: u-boot@lists.denx.de

On Friday, November 20, 2015 at 07:41:30 PM, Jan Viktorin wrote:
> On Fri, 20 Nov 2015 17:27:02 +0100
> 
> Marek Vasut <marex@denx.de> wrote:
> > On Friday, November 20, 2015 at 05:21:08 PM, Marek Vasut wrote:
> > > On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote:
> > > > Hello Marek and U-Boot community,
> > > 
> > > [snip]
> > > 
> > > > So, what is the status of the SPL for SoCFPGA in upstream? Does
> > > > anybody test all the claimed socfpga platforms?
> > > 
> > > I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna
> > > look at the CV SoCDK issue ? I might be able to set it up later this
> > > weekend, but don't hold your breath, I am pretty overloaded.
> > 
> > Update, my SoCdk boots just fine:
> > 
> > U-Boot SPL 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50)
> > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> > drivers/ddr/altera/sequencer.c: Calibration complete
> > Trying to boot from MMC
> > 
> > 
> > U-Boot 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50 +0100)
> > 
> > CPU:   Altera SoCFPGA Platform
> > FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> > BOOT:  SD/MMC External Transceiver (1.8V)
> > 
> >        Watchdog enabled
> > 
> > I2C:   ready
> > DRAM:  1 GiB
> > MMC:   SOCFPGA DWMMC: 0
> > *** Warning - bad CRC, using default environment
> > 
> > In:    serial
> > Out:   serial
> > Err:   serial
> > Model: Altera SOCFPGA Cyclone V SoC Development Kit
> > Net:   No ethernet found.
> > Hit any key to stop autoboot:  0
> > =>
> > 
> > Best regards,
> > Marek Vasut
> 
> Hi, thanks for quick replies.
> 
> I tried the SoCDK with 2016-rc1 and the default config
> socfpga_cyclone5_defconfig. The previous build has used some
> customization of the config (I tried to disable EMAC). I build
> by the Buildroot using the uclibc toolchain. Installed as
> 
> $ sudo dd if=u-boot-spl-dtb.bin.crc of=/dev/sdc1 bs=64k seek=0
> $ sudo dd if=u-boot-dtb.img of=/dev/sdc1 bs=64k seek=4

Do the following, the u-boot-with-spl-dtb.sfp is automatically generated
by the build in 2016.01rc, while you need to do make u-boot-with-spl-dtb.sfp
with 2015.10. This is actually important:

$ sudo dd if=u-boot-with-spl-dtb.sfp of=/dev/sdc

btw which version of gcc does your toolchain use ? It might be a compiler
bug, I've seen those more than once.

> Freezed again:
> 
> U-Boot SPL 2016.01-rc1 (Nov 20 2015 - 17:49:39)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> 
> 
> U-Boot 2016.01-rc1 (Nov 20 2015 - 17:49:39 +0100)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT:  SD/MMC Internal Transceiver (3.0V)
>        Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SOCFPGA DWMMC: 0
> *** Warning - bad CRC, using default environment
> 
> In:    serial
> Out:   serial
> Err:   serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> [...freezed...]
> 
> Regards
> Jan Viktorin

Best regards,
Marek Vasut