From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 26 Nov 2015 02:26:30 +0100 Subject: [U-Boot] [PATCH v2] mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts In-Reply-To: <1448500204-2969-1-git-send-email-clsee@altera.com> References: <1448500204-2969-1-git-send-email-clsee@altera.com> Message-ID: <201511260226.30199.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday, November 26, 2015 at 02:10:04 AM, Chin Liang See wrote: > socfpga_dw_mmc driver will obtain the drvsel and > smplsel value from device tree instead of definition > in config header file. > > Signed-off-by: Chin Liang See > Cc: Dinh Nguyen > Cc: Dinh Nguyen > Cc: Pavel Machek > Cc: Marek Vasut > Cc: Stefan Roese > Cc: Pantelis Antoniou > Cc: Simon Glass > Cc: Jaehoon Chung > --- > Changes for v2 > - Put default value for drvsel to 3 in case node in DT missing > - Remove unnecessary ad-hoc vairable > - Free up first calloc if second calloc failed > --- > arch/arm/dts/socfpga_cyclone5.dtsi | 2 ++ > drivers/mmc/socfpga_dw_mmc.c | 22 ++++++++++++++++++++-- > include/configs/socfpga_common.h | 2 -- > 3 files changed, 22 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi > b/arch/arm/dts/socfpga_cyclone5.dtsi index de36209..040b236 100644 > --- a/arch/arm/dts/socfpga_cyclone5.dtsi > +++ b/arch/arm/dts/socfpga_cyclone5.dtsi > @@ -25,6 +25,8 @@ > bus-width = <4>; > cap-mmc-highspeed; > cap-sd-highspeed; > + drvsel = <3>; > + smplsel = <0>; > }; > > sysmgr at ffd08000 { I'm not very fond of bunding DT changes and driver changes together, these should be separate, so it'd be nice if you sent a V3 and split this into two patches. Otherwise Acked-by: Marek Vasut > diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c > index 8076761..38eb783 100644 > --- a/drivers/mmc/socfpga_dw_mmc.c > +++ b/drivers/mmc/socfpga_dw_mmc.c > @@ -19,18 +19,25 @@ static const struct socfpga_clock_manager > *clock_manager_base = static const struct socfpga_system_manager > *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; > > +/* socfpga implmentation specific drver private data */ > +struct dwmci_socfpga_priv_data { > + unsigned int drvsel; > + unsigned int smplsel; > +}; > + > static void socfpga_dwmci_clksel(struct dwmci_host *host) > { > unsigned int drvsel; > unsigned int smplsel; > + struct dwmci_socfpga_priv_data *priv = host->priv; > > /* Disable SDMMC clock. */ > clrbits_le32(&clock_manager_base->per_pll.en, > CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); > > /* Configures drv_sel and smpl_sel */ > - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; > - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; > + drvsel = priv->drvsel; > + smplsel = priv->smplsel; You can probably just use priv->xxx directly in the code and drop those vars. > debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); > writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), [...]