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* [U-Boot] [PATCH v1] arm: socfpga: Enable load zImage and Linux DTB from QSPI
@ 2015-11-26  2:32 Chin Liang See
  2015-11-26  6:12 ` Stefan Roese
  2015-11-26 14:43 ` Pavel Machek
  0 siblings, 2 replies; 14+ messages in thread
From: Chin Liang See @ 2015-11-26  2:32 UTC (permalink / raw)
  To: u-boot

Adding new environment qspiload which will load zImage and
Linux DTB from serial NOR flash. The default flash offset for
the images as below and they are configurable during run time.

- zImage located at 0xa0000 with assuming file size 6MB
- Linux DTB located at 0x50000 with assuming file size 28kB

Please adjust the file size env var if exceeding the default

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
 include/configs/socfpga_arria5_socdk.h   | 10 +++++++++-
 include/configs/socfpga_cyclone5_socdk.h | 10 +++++++++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 91ecbf7..0506336 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -77,9 +77,11 @@
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
+	"bootimagesize=0x600000\0" \
 	"fdt_addr=100\0" \
 	"fdtimage=socfpga.dtb\0" \
-		"fsloadcmd=ext2load\0" \
+	"fdtimagesize=0x7000\0" \
+	"fsloadcmd=ext2load\0" \
 	"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"mmcroot=/dev/mmcblk0p2\0" \
 	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
@@ -90,6 +92,12 @@
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
+	"qspiloadcs=0\0" \
+	"qspibootimageaddr=0xa0000\0" \
+	"qspifdtaddr=0x50000\0" \
+	"qspiload=sf probe ${qspiloadcs};" \
+		"sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \
+		"sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize};\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index b5cf393..d7369ee 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -77,9 +77,11 @@
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
+	"bootimagesize=0x600000\0" \
 	"fdt_addr=100\0" \
 	"fdtimage=socfpga.dtb\0" \
-		"fsloadcmd=ext2load\0" \
+	"fdtimagesize=0x7000\0" \
+	"fsloadcmd=ext2load\0" \
 	"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"mmcroot=/dev/mmcblk0p2\0" \
 	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
@@ -90,6 +92,12 @@
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
+	"qspiloadcs=0\0" \
+	"qspibootimageaddr=0xa0000\0" \
+	"qspifdtaddr=0x50000\0" \
+	"qspiload=sf probe ${qspiloadcs};" \
+		"sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \
+		"sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize};\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
-- 
2.2.0


From clsee at ubuntu  Thu Nov 26 01:37:35 2015
From: clsee at ubuntu (clsee)
Date: Thu, 26 Nov 2015 08:37:35 +0800
Subject: [U-Boot] [PATCH] mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts
Message-ID: <1448498255-2505-1-git-send-email-user@ubuntu>

From: Chin Liang See <clsee@altera.com>

socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
 arch/arm/dts/socfpga_cyclone5.dtsi |  2 ++
 drivers/mmc/socfpga_dw_mmc.c       | 24 ++++++++++++++++++++++--
 include/configs/socfpga_common.h   |  2 --
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
index de36209..040b236 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -25,6 +25,8 @@
 			bus-width = <4>;
 			cap-mmc-highspeed;
 			cap-sd-highspeed;
+			drvsel = <3>;
+			smplsel = <0>;
 		};
 
 		sysmgr at ffd08000 {
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8076761..2cd7a51 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -19,18 +19,25 @@ static const struct socfpga_clock_manager *clock_manager_base =
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
+/* socfpga implmentation specific drver private data */
+struct dwmci_socfpga_priv_data {
+	unsigned int drvsel;
+	unsigned int smplsel;
+};
+
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	unsigned int drvsel;
 	unsigned int smplsel;
+	struct dwmci_socfpga_priv_data *priv = host->priv;
 
 	/* Disable SDMMC clock. */
 	clrbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
 	/* Configures drv_sel and smpl_sel */
-	drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
-	smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
+	drvsel = priv->drvsel;
+	smplsel = priv->smplsel;
 
 	debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
 	writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
@@ -50,8 +57,10 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 	const unsigned long clk = cm_get_mmc_controller_clk_hz();
 
 	struct dwmci_host *host;
+	struct dwmci_socfpga_priv_data *priv;
 	fdt_addr_t reg_base;
 	int bus_width, fifo_depth;
+	unsigned int drvsel, smplsel;
 
 	if (clk == 0) {
 		printf("DWMMC%d: MMC clock is zero!", idx);
@@ -78,11 +87,19 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 		return -EINVAL;
 	}
 
+	drvsel = fdtdec_get_uint(blob, node, "drvsel", 0);
+	smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+
 	/* Allocate the host */
 	host = calloc(1, sizeof(*host));
 	if (!host)
 		return -ENOMEM;
 
+	/* Allocate the priv */
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+
 	host->name = "SOCFPGA DWMMC";
 	host->ioaddr = (void *)reg_base;
 	host->buswidth = bus_width;
@@ -92,6 +109,9 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 	host->bus_hz = clk;
 	host->fifoth_val = MSIZE(0x2) |
 		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+	priv->drvsel = drvsel;
+	priv->smplsel = smplsel;
+	host->priv = priv;
 
 	return add_dwmci(host, host->bus_hz, 400000);
 }
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f6808b5..b661cc2 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -153,8 +153,6 @@
 #define CONFIG_DWMMC
 #define CONFIG_SOCFPGA_DWMMC
 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
-- 
2.2.0

^ permalink raw reply related	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2015-11-27 14:24 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-11-26  2:32 [U-Boot] [PATCH v1] arm: socfpga: Enable load zImage and Linux DTB from QSPI Chin Liang See
2015-11-26  6:12 ` Stefan Roese
2015-11-27  1:26   ` Chin Liang See
2015-11-26 14:43 ` Pavel Machek
2015-11-27  1:24   ` Chin Liang See
2015-11-27  1:27     ` Marek Vasut
2015-11-27  1:34       ` Chin Liang See
2015-11-27 10:20         ` Marek Vasut
2015-11-27 12:07           ` Chin Liang See
2015-11-27 12:11             ` Marek Vasut
2015-11-27 12:16               ` Chin Liang See
2015-11-27 12:26                 ` Marek Vasut
2015-11-27 13:08                   ` Chin Liang See
2015-11-27 14:24                     ` Marek Vasut

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