* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 @ 2015-07-27 20:34 Marek Vasut 2015-08-04 10:12 ` Marek Vasut 2015-12-01 17:23 ` Marek Vasut 0 siblings, 2 replies; 8+ messages in thread From: Marek Vasut @ 2015-07-27 20:34 UTC (permalink / raw) To: u-boot Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> --- arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -16,6 +16,23 @@ #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 #ifndef CONFIG_SYS_DCACHE_OFF +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + /* * Write the level and type you want to Cache Size Selection Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) */ void flush_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); v7_outer_cache_flush_range(start, stop); -- 2.1.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2015-07-27 20:34 [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 Marek Vasut @ 2015-08-04 10:12 ` Marek Vasut 2015-12-01 17:23 ` Marek Vasut 1 sibling, 0 replies; 8+ messages in thread From: Marek Vasut @ 2015-08-04 10:12 UTC (permalink / raw) To: u-boot On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > Add code to aid tracking down cache alignment issues. > In case DEBUG is defined in the cache.c, this code will > check alignment of each attempt to flush/invalidate data > cache and print a warning if the alignment is incorrect. > If DEBUG is not defined, this code is optimized out. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > Cc: Tom Rini <trini@konsulko.com> Bump ? Is this patch useful or shall it be dropped ? > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c > index e8ee875..84431bb 100644 > --- a/arch/arm/cpu/armv7/cache_v7.c > +++ b/arch/arm/cpu/armv7/cache_v7.c > @@ -16,6 +16,23 @@ > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > #ifndef CONFIG_SYS_DCACHE_OFF > +static int check_cache_range(unsigned long start, unsigned long stop) > +{ > + int ok = 1; > + > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > + ok = 0; > + > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > + ok = 0; > + > + if (!ok) > + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", > + start, stop); > + > + return ok; > +} > + > /* > * Write the level and type you want to Cache Size Selection > Register(CSSELR) * to get size details from Current Cache Size ID > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > */ > void invalidate_dcache_range(unsigned long start, unsigned long stop) > { > + check_cache_range(start, stop); > + > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > v7_outer_cache_inval_range(start, stop); > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > unsigned long stop) */ > void flush_dcache_range(unsigned long start, unsigned long stop) > { > + check_cache_range(start, stop); > + > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > v7_outer_cache_flush_range(start, stop); Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2015-07-27 20:34 [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 Marek Vasut 2015-08-04 10:12 ` Marek Vasut @ 2015-12-01 17:23 ` Marek Vasut 2015-12-11 4:36 ` Marek Vasut 1 sibling, 1 reply; 8+ messages in thread From: Marek Vasut @ 2015-12-01 17:23 UTC (permalink / raw) To: u-boot On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > Add code to aid tracking down cache alignment issues. > In case DEBUG is defined in the cache.c, this code will > check alignment of each attempt to flush/invalidate data > cache and print a warning if the alignment is incorrect. > If DEBUG is not defined, this code is optimized out. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > Cc: Tom Rini <trini@konsulko.com> Bump ? > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c > index e8ee875..84431bb 100644 > --- a/arch/arm/cpu/armv7/cache_v7.c > +++ b/arch/arm/cpu/armv7/cache_v7.c > @@ -16,6 +16,23 @@ > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > #ifndef CONFIG_SYS_DCACHE_OFF > +static int check_cache_range(unsigned long start, unsigned long stop) > +{ > + int ok = 1; > + > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > + ok = 0; > + > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > + ok = 0; > + > + if (!ok) > + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", > + start, stop); > + > + return ok; > +} > + > /* > * Write the level and type you want to Cache Size Selection > Register(CSSELR) * to get size details from Current Cache Size ID > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > */ > void invalidate_dcache_range(unsigned long start, unsigned long stop) > { > + check_cache_range(start, stop); > + > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > v7_outer_cache_inval_range(start, stop); > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > unsigned long stop) */ > void flush_dcache_range(unsigned long start, unsigned long stop) > { > + check_cache_range(start, stop); > + > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > v7_outer_cache_flush_range(start, stop); Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2015-12-01 17:23 ` Marek Vasut @ 2015-12-11 4:36 ` Marek Vasut 2015-12-28 15:23 ` Marek Vasut 0 siblings, 1 reply; 8+ messages in thread From: Marek Vasut @ 2015-12-11 4:36 UTC (permalink / raw) To: u-boot On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote: > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > > Add code to aid tracking down cache alignment issues. > > In case DEBUG is defined in the cache.c, this code will > > check alignment of each attempt to flush/invalidate data > > cache and print a warning if the alignment is incorrect. > > If DEBUG is not defined, this code is optimized out. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > Cc: Tom Rini <trini@konsulko.com> > > Bump ? Bump ? > > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > > > diff --git a/arch/arm/cpu/armv7/cache_v7.c > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 > > --- a/arch/arm/cpu/armv7/cache_v7.c > > +++ b/arch/arm/cpu/armv7/cache_v7.c > > @@ -16,6 +16,23 @@ > > > > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > > > #ifndef CONFIG_SYS_DCACHE_OFF > > > > +static int check_cache_range(unsigned long start, unsigned long stop) > > +{ > > + int ok = 1; > > + > > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > + ok = 0; > > + > > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > + ok = 0; > > + > > + if (!ok) > > + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", > > + start, stop); > > + > > + return ok; > > +} > > + > > > > /* > > > > * Write the level and type you want to Cache Size Selection > > > > Register(CSSELR) * to get size details from Current Cache Size ID > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > > > > */ > > > > void invalidate_dcache_range(unsigned long start, unsigned long stop) > > { > > > > + check_cache_range(start, stop); > > + > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > > > v7_outer_cache_inval_range(start, stop); > > > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > > unsigned long stop) */ > > > > void flush_dcache_range(unsigned long start, unsigned long stop) > > { > > > > + check_cache_range(start, stop); > > + > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > > > v7_outer_cache_flush_range(start, stop); > > Best regards, > Marek Vasut ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2015-12-11 4:36 ` Marek Vasut @ 2015-12-28 15:23 ` Marek Vasut 2016-01-24 17:28 ` Marek Vasut 0 siblings, 1 reply; 8+ messages in thread From: Marek Vasut @ 2015-12-28 15:23 UTC (permalink / raw) To: u-boot On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote: > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote: > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > > > Add code to aid tracking down cache alignment issues. > > > In case DEBUG is defined in the cache.c, this code will > > > check alignment of each attempt to flush/invalidate data > > > cache and print a warning if the alignment is incorrect. > > > If DEBUG is not defined, this code is optimized out. > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > > Cc: Tom Rini <trini@konsulko.com> > > > > Bump ? > > Bump ? Bump #3 ? > > > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > > > 1 file changed, 21 insertions(+) > > > > > > diff --git a/arch/arm/cpu/armv7/cache_v7.c > > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 > > > --- a/arch/arm/cpu/armv7/cache_v7.c > > > +++ b/arch/arm/cpu/armv7/cache_v7.c > > > @@ -16,6 +16,23 @@ > > > > > > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > > > > > #ifndef CONFIG_SYS_DCACHE_OFF > > > > > > +static int check_cache_range(unsigned long start, unsigned long stop) > > > +{ > > > + int ok = 1; > > > + > > > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > + ok = 0; > > > + > > > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > + ok = 0; > > > + > > > + if (!ok) > > > + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", > > > + start, stop); > > > + > > > + return ok; > > > +} > > > + > > > > > > /* > > > > > > * Write the level and type you want to Cache Size Selection > > > > > > Register(CSSELR) * to get size details from Current Cache Size ID > > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > > > > > > */ > > > > > > void invalidate_dcache_range(unsigned long start, unsigned long stop) > > > { > > > > > > + check_cache_range(start, stop); > > > + > > > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > > > > > v7_outer_cache_inval_range(start, stop); > > > > > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > > > unsigned long stop) */ > > > > > > void flush_dcache_range(unsigned long start, unsigned long stop) > > > { > > > > > > + check_cache_range(start, stop); > > > + > > > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > > > > > v7_outer_cache_flush_range(start, stop); > > > > Best regards, > > Marek Vasut Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2015-12-28 15:23 ` Marek Vasut @ 2016-01-24 17:28 ` Marek Vasut 2016-01-25 16:04 ` Tom Rini 0 siblings, 1 reply; 8+ messages in thread From: Marek Vasut @ 2016-01-24 17:28 UTC (permalink / raw) To: u-boot On Monday, December 28, 2015 at 04:23:46 PM, Marek Vasut wrote: > On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote: > > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote: > > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > > > > Add code to aid tracking down cache alignment issues. > > > > In case DEBUG is defined in the cache.c, this code will > > > > check alignment of each attempt to flush/invalidate data > > > > cache and print a warning if the alignment is incorrect. > > > > If DEBUG is not defined, this code is optimized out. > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > > > Cc: Tom Rini <trini@konsulko.com> > > > > > > Bump ? > > > > Bump ? > > Bump #3 ? Bump #4 ? > > > > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > > > > 1 file changed, 21 insertions(+) > > > > > > > > diff --git a/arch/arm/cpu/armv7/cache_v7.c > > > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 > > > > --- a/arch/arm/cpu/armv7/cache_v7.c > > > > +++ b/arch/arm/cpu/armv7/cache_v7.c > > > > @@ -16,6 +16,23 @@ > > > > > > > > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > > > > > > > #ifndef CONFIG_SYS_DCACHE_OFF > > > > > > > > +static int check_cache_range(unsigned long start, unsigned long > > > > stop) +{ > > > > + int ok = 1; > > > > + > > > > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > > + ok = 0; > > > > + > > > > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > > + ok = 0; > > > > + > > > > + if (!ok) > > > > + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", > > > > + start, stop); > > > > + > > > > + return ok; > > > > +} > > > > + > > > > > > > > /* > > > > > > > > * Write the level and type you want to Cache Size Selection > > > > > > > > Register(CSSELR) * to get size details from Current Cache Size ID > > > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > > > > > > > > */ > > > > > > > > void invalidate_dcache_range(unsigned long start, unsigned long > > > > stop) { > > > > > > > > + check_cache_range(start, stop); > > > > + > > > > > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > > > > > > > v7_outer_cache_inval_range(start, stop); > > > > > > > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > > > > unsigned long stop) */ > > > > > > > > void flush_dcache_range(unsigned long start, unsigned long stop) > > > > { > > > > > > > > + check_cache_range(start, stop); > > > > + > > > > > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > > > > > > > v7_outer_cache_flush_range(start, stop); > > > > > > Best regards, > > > Marek Vasut > > Best regards, > Marek Vasut Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2016-01-24 17:28 ` Marek Vasut @ 2016-01-25 16:04 ` Tom Rini 2016-01-25 21:22 ` Albert ARIBAUD 0 siblings, 1 reply; 8+ messages in thread From: Tom Rini @ 2016-01-25 16:04 UTC (permalink / raw) To: u-boot On Sun, Jan 24, 2016 at 06:28:12PM +0100, Marek Vasut wrote: > On Monday, December 28, 2015 at 04:23:46 PM, Marek Vasut wrote: > > On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote: > > > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote: > > > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > > > > > Add code to aid tracking down cache alignment issues. > > > > > In case DEBUG is defined in the cache.c, this code will > > > > > check alignment of each attempt to flush/invalidate data > > > > > cache and print a warning if the alignment is incorrect. > > > > > If DEBUG is not defined, this code is optimized out. > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > > > > Cc: Tom Rini <trini@konsulko.com> > > > > > > > > Bump ? > > > > > > Bump ? > > > > Bump #3 ? > > Bump #4 ? Albert? > > > > > arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ > > > > > 1 file changed, 21 insertions(+) > > > > > > > > > > diff --git a/arch/arm/cpu/armv7/cache_v7.c > > > > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 > > > > > --- a/arch/arm/cpu/armv7/cache_v7.c > > > > > +++ b/arch/arm/cpu/armv7/cache_v7.c > > > > > @@ -16,6 +16,23 @@ > > > > > > > > > > #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 > > > > > > > > > > #ifndef CONFIG_SYS_DCACHE_OFF > > > > > > > > > > +static int check_cache_range(unsigned long start, unsigned long > > > > > stop) +{ > > > > > + int ok = 1; > > > > > + > > > > > + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > > > + ok = 0; > > > > > + > > > > > + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) > > > > > + ok = 0; > > > > > + > > > > > + if (!ok) > > > > > + debug("CACHE: Misaligned operation at range [%08lx, > %08lx]\n", > > > > > + start, stop); > > > > > + > > > > > + return ok; > > > > > +} > > > > > + > > > > > > > > > > /* > > > > > > > > > > * Write the level and type you want to Cache Size Selection > > > > > > > > > > Register(CSSELR) * to get size details from Current Cache Size ID > > > > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) > > > > > > > > > > */ > > > > > > > > > > void invalidate_dcache_range(unsigned long start, unsigned long > > > > > stop) { > > > > > > > > > > + check_cache_range(start, stop); > > > > > + > > > > > > > > > > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > > > > > > > > > v7_outer_cache_inval_range(start, stop); > > > > > > > > > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, > > > > > unsigned long stop) */ > > > > > > > > > > void flush_dcache_range(unsigned long start, unsigned long stop) > > > > > { > > > > > > > > > > + check_cache_range(start, stop); > > > > > + > > > > > > > > > > v7_dcache_maint_range(start, stop, > ARMV7_DCACHE_CLEAN_INVAL_RANGE); > > > > > > > > > > v7_outer_cache_flush_range(start, stop); > > > > > > > > Best regards, > > > > Marek Vasut > > > > Best regards, > > Marek Vasut > > Best regards, > Marek Vasut > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160125/51dc51a3/attachment.sig> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 2016-01-25 16:04 ` Tom Rini @ 2016-01-25 21:22 ` Albert ARIBAUD 0 siblings, 0 replies; 8+ messages in thread From: Albert ARIBAUD @ 2016-01-25 21:22 UTC (permalink / raw) To: u-boot Hello Tom, On Mon, 25 Jan 2016 11:04:59 -0500, Tom Rini <trini@konsulko.com> wrote: > On Sun, Jan 24, 2016 at 06:28:12PM +0100, Marek Vasut wrote: > > On Monday, December 28, 2015 at 04:23:46 PM, Marek Vasut wrote: > > > On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote: > > > > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote: > > > > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote: > > > > > > Add code to aid tracking down cache alignment issues. > > > > > > In case DEBUG is defined in the cache.c, this code will > > > > > > check alignment of each attempt to flush/invalidate data > > > > > > cache and print a warning if the alignment is incorrect. > > > > > > If DEBUG is not defined, this code is optimized out. > > > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > > > > > Cc: Tom Rini <trini@konsulko.com> > > > > > > > > > > Bump ? > > > > > > > > Bump ? > > > > > > Bump #3 ? > > > > Bump #4 ? > > Albert? Sorry. Applied to u-boot-arm/master, thanks. Amicalement, -- Albert. ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-01-25 21:22 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-07-27 20:34 [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 Marek Vasut 2015-08-04 10:12 ` Marek Vasut 2015-12-01 17:23 ` Marek Vasut 2015-12-11 4:36 ` Marek Vasut 2015-12-28 15:23 ` Marek Vasut 2016-01-24 17:28 ` Marek Vasut 2016-01-25 16:04 ` Tom Rini 2016-01-25 21:22 ` Albert ARIBAUD
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