[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

[Marek Vasut <marex@denx.de>]

On Tuesday, December 01, 2015 at 05:48:32 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the defines for the reset manager and some basic reset functionality.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: integrate into a5/c5 reset manager

[...]

Hi!

> diff --git a/arch/arm/mach-socfpga/reset_manager.c
> b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..b955d39 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager.c
> @@ -18,7 +18,51 @@ static const struct socfpga_reset_manager
> *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> 
> -/* Assert or de-assert SoCFPGA reset manager reset. */
> +/*
> + * Assert or de-assert SoCFPGA reset manager reset.
> + */
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +void socfpga_per_reset(u32 reset, int set)
> +{
> +	const void *reg;

OK, Dinh, come on. I know you _can_ do better than this crap.

> +	if (RSTMGR_BANK(reset) == 0)
> +		reg = &reset_manager_base->mpu_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 1)
> +		reg = &reset_manager_base->per0_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 2)
> +		reg = &reset_manager_base->per1_mod_rst;

The only difference between gen5 and gen10 in this function is the register 
naming. On gen5, these two registers are called per_mod_rst and per2_mod_rst,
while on gen10, they are called per0_mod_rst and per1_mod_rst . Do you really
think such a trivial change justifies introducing a whole new copy of this
function ?

> +	else if (RSTMGR_BANK(reset) == 3)
> +		reg = &reset_manager_base->brg_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 4)
> +		reg = &reset_manager_base->sys_mod_rst;
> +	else    /* Invalid reset register, do nothing */
> +		return;
> +
> +	if (set)
> +		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> +	else
> +		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> +}
> +
> +/*
> + * Disable all the peripherals except L4 watchdog0 and L4 Timer 0.
> + */
> +void reset_assert_all_peripherals_except_l4wd0_l4timer0(void)
> +{
> +	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
> +			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> +
> +	unsigned mask_ecc_ocp = 0x0000FF00;
> +
> +	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> +	writel(~l4wd0, &reset_manager_base->per1_mod_rst);
> +	setbits_le32(&reset_manager_base->per0_mod_rst, ~mask_ecc_ocp);
> +
> +	/* Finally disable the ECC_OCP */
> +	setbits_le32(&reset_manager_base->per0_mod_rst, mask_ecc_ocp);
> +}
> +#else
>  void socfpga_per_reset(u32 reset, int set)
>  {
>  	const void *reg;
> @@ -118,3 +162,4 @@ void socfpga_bridges_reset(int enable)
>  	}
>  }
>  #endif
> +#endif