[U-Boot] [PATCHv3 7/9] arm: socfpga: arria10: add config option build for arria10

[Marek Vasut <marex@denx.de>]

On Wednesday, December 02, 2015 at 07:12:54 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: none
> ---
>  arch/arm/Kconfig              |  4 ++--
>  arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 408e4ff..c43c8b4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -500,9 +500,9 @@ config RMOBILE
>  config ARCH_SOCFPGA
>  	bool "Altera SOCFPGA family"
>  	select CPU_V7
> -	select SUPPORT_SPL
> +	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
>  	select OF_CONTROL
> -	select SPL_OF_CONTROL
> +	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
>  	select DM
>  	select DM_SPI_FLASH
>  	select DM_SPI
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 4ea171a..0d2d8d6 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -1,5 +1,8 @@
>  if ARCH_SOCFPGA
> 
> +config TARGET_SOCFPGA_ARRIA10
> +	bool
> +

This should go below ARRIA5 to keep thing sorted numerically.

>  config TARGET_SOCFPGA_ARRIA5
>  	bool
>  	select SOCFPGA_GEN5
> @@ -23,6 +26,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	bool "Altera SOCFPGA SoCDK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
> 
> +config TARGET_SOCFPGA_ARRIA10_SOCDK
> +	bool "Altera SOCFPGA SoCDK (Arria 10)"
> +	select TARGET_SOCFPGA_ARRIA10
> +
>  config TARGET_SOCFPGA_DENX_MCVEVK
>  	bool "DENX MCVEVK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
> @@ -47,6 +54,7 @@ endchoice
> 
>  config SYS_BOARD
>  	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
> @@ -56,6 +64,7 @@ config SYS_BOARD
> 
>  config SYS_VENDOR
>  	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
>  	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
> @@ -67,6 +76,7 @@ config SYS_SOC
> 
>  config SYS_CONFIG_NAME
>  	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK