[U-Boot] [PATCHv2 0/9] ARM: socfpga: Add minimal support for Arria10

[U-Boot] [PATCHv2 0/9] ARM: socfpga: Add minimal support for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Hi,

This is v2 of the patch series that adds minimal support for Altera's Arria10
platform.

v2:
- Removes the need for a separate /mach-socfpga/arria10 directory
- Tries to re-use alot of the Arria5/Cyclone5 code
- Removes the usage of unions bitfields in the SDRAM defines

v1:
The series builds for
the Altera Arria10 SoCDK, but is not entirely functional on the hardware yet.
This series really just add the defines, build and Kconfig layout for Arria10.

There are few TODO after this series:
- Add DTS file for the devkit
- Add clock manager
- The Arria10 Pin Mux requires the FPGA to get programmed before the SDRAM
  controller can be usable. So another patch is needed to make use of the fpga
  manager to program the FPGA within the limited size of the OCRAM.

Thanks,
Dinh


Dinh Nguyen (9):
  arm: socfpga: arria10: add system manager defines
  arm: socfpga: arria10: add reset manager for Arria10
  arm: socfpga: arria10: add sdram defines for Arria10
  arm: socfpga: arria10: add misc functions for Arria10
  arm: socfpga: arria10: add socfpga_arria10_socdk config
  arm: socfpga: arria10: add board files for the Arria10 SoCDK
  arm: socfpga: arria10: add socfpga_arria10_defconfig
  arm: socfpga: arria10: add config option build for arria10
  arm: socfpga: remove building scan manager

 arch/arm/Kconfig                                   |   4 +-
 arch/arm/mach-socfpga/Kconfig                      |  10 +
 arch/arm/mach-socfpga/Makefile                     |   7 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  66 ++++
 arch/arm/mach-socfpga/include/mach/sdram_a10.h     | 380 +++++++++++++++++++++
 .../mach-socfpga/include/mach/system_manager_a10.h | 157 +++++++++
 arch/arm/mach-socfpga/misc.c                       |  56 ++-
 arch/arm/mach-socfpga/reset_manager.c              |  47 ++-
 board/altera/arria10-socdk/Kconfig                 |  18 +
 board/altera/arria10-socdk/Makefile                |   7 +
 board/altera/arria10-socdk/socfpga.c               |  24 ++
 configs/socfpga_arria10_defconfig                  |  11 +
 include/configs/socfpga_arria10_socdk.h            | 157 +++++++++
 13 files changed, 937 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_a10.h
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

-- 
2.6.2

[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: clean up parenthesis
---
 .../mach-socfpga/include/mach/system_manager_a10.h | 157 +++++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_a10.h b/arch/arm/mach-socfpga/include/mach/system_manager_a10.h
new file mode 100644
index 0000000..81fd2f2
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_a10.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_SOCFPGA_SYSTEM_MANAGER_A10_H_
+#define	_SOCFPGA_SYSTEM_MANAGER_A10_H_
+
+#ifndef __ASSEMBLY__
+struct socfpga_system_manager {
+	u32  siliconid1;
+	u32  siliconid2;
+	u32  wddbg;
+	u32  bootinfo;
+	u32  mpu_ctrl_l2_ecc;
+	u32  _pad_0x14_0x1f[3];
+	u32  dma;
+	u32  dma_periph;
+	u32  sdmmcgrp_ctrl;
+	u32  sdmmc_l3master;
+	u32  nand_bootstrap;
+	u32  nand_l3master;
+	u32  usb0_l3master;
+	u32  usb1_l3master;
+	u32  emac_global;
+	u32  emac0;
+	u32  emac1;
+	u32  emac2;
+	u32  _pad_0x50_0x5f[4];
+	u32  fpgaintf_en_global;
+	u32  fpgaintf_en_0;
+	u32  fpgaintf_en_1;
+	u32  fpgaintf_en_2;
+	u32  fpgaintf_en_3;
+	u32  _pad_0x74_0x7f[3];
+	u32  noc_addr_remap_value;
+	u32  noc_addr_remap_set;
+	u32  noc_addr_remap_clear;
+	u32  _pad_0x8c_0x8f;
+	u32  ecc_intmask_value;
+	u32  ecc_intmask_set;
+	u32  ecc_intmask_clr;
+	u32  ecc_intstatus_serr;
+	u32  ecc_intstatus_derr;
+	u32  mpu_status_l2_ecc;
+	u32  mpu_clear_l2_ecc;
+	u32  mpu_status_l1_parity;
+	u32  mpu_clear_l1_parity;
+	u32  mpu_set_l1_parity;
+	u32  _pad_0xb8_0xbf[2];
+	u32  noc_timeout;
+	u32  noc_idlereq_set;
+	u32  noc_idlereq_clr;
+	u32  noc_idlereq_value;
+	u32  noc_idleack;
+	u32  noc_idlestatus;
+	u32  fpga2soc_ctrl;
+	u32  _pad_0xdc_0xff[9];
+	u32  tsmc_tsel_0;
+	u32  tsmc_tsel_1;
+	u32  tsmc_tsel_2;
+	u32  tsmc_tsel_3;
+	u32  _pad_0x110_0x200[60];
+	u32  romhw_ctrl;
+	u32  romcode_ctrl;
+	u32  romcode_cpu1startaddr;
+	u32  romcode_initswstate;
+	u32  romcode_initswlastld;
+	u32  _pad_0x214_0x217;
+	u32  warmram_enable;
+	u32  warmram_datastart;
+	u32  warmram_length;
+	u32  warmram_execution;
+	u32  warmram_crc;
+	u32  _pad_0x22c_0x22f;
+	u32  isw_handoff[8];
+	u32  romcode_bootromswstate[8];
+};
+#endif /* __ASSEMBLY__ */
+
+/* bit fields */
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		(1<<0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		(1<<1)
+#define SYSMGR_ECC_OCRAM_EN		(1<<0)
+#define SYSMGR_ECC_OCRAM_SERR		(1<<3)
+#define SYSMGR_ECC_OCRAM_DERR		(1<<4)
+#define SYSMGR_FPGAINTF_USEFPGA		0x1
+#define SYSMGR_FPGAINTF_SPIM0		(1<<0)
+#define SYSMGR_FPGAINTF_SPIM1		(1<<1)
+#define SYSMGR_FPGAINTF_EMAC0		(1<<2)
+#define SYSMGR_FPGAINTF_EMAC1		(1<<3)
+#define SYSMGR_FPGAINTF_NAND		(1<<4)
+#define SYSMGR_FPGAINTF_SDMMC		(1<<5)
+
+/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum                        */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V		0x0
+#define VOLTAGE_SEL_1P8V	0x1
+#define VOLTAGE_SEL_2P5V	0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE	0
+#define INPUT_BUF_1P8V		1
+#define INPUT_BUF_2P5V3V	2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE		0
+#define WK_PU_ENABLE		1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW		0
+#define PU_SLW_RT_FAST		1
+#define PU_SLW_RT_DEFAULT	PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW		0
+#define PD_SLW_RT_FAST		1
+#define PD_SLW_RT_DEFAULT	PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT	0x10
+#define PD_DRV_STRG_DEFAULT	0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB		0
+#define PD_SLW_RT_LSB		5
+#define PU_DRV_STRG_LSB		8
+#define PU_SLW_RT_LSB		13
+#define WK_PU_LSB		16
+#define INPUT_BUF_LSB		17
+#define BIAS_TRIM_LSB		19
+#define VOLTAGE_SEL_LSB		0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK	0x00000001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK	0x00000010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK	0x00000100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK	0x00010000
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK	0x00100000
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK	0x01000000
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK	0x00000001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK    0x00000002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK    0x00000002
+
+#define SYSMGR_A10_SDMMC_CTRL_SET(smplsel, drvsel)	\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 4) & 0x70))
+
+#endif /* _SOCFPGA_SYSTEM_MANAGER_A10_H_ */
-- 
2.6.2

[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:31 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add system manager defines for Arria10.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: clean up parenthesis

[...]

> +/* bit fields */
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		(1<<0)
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		(1<<1)
> +#define SYSMGR_ECC_OCRAM_EN		(1<<0)
> +#define SYSMGR_ECC_OCRAM_SERR		(1<<3)
> +#define SYSMGR_ECC_OCRAM_DERR		(1<<4)

Uh, so you have SYSMGR_FPGAINTF_USEFPGA and _SPIM0 here, which use the same
bit. How is this supposed to work ? Is this some specialty of A10 ?

> +#define SYSMGR_FPGAINTF_USEFPGA		0x1
> +#define SYSMGR_FPGAINTF_SPIM0		(1<<0)
> +#define SYSMGR_FPGAINTF_SPIM1		(1<<1)
> +#define SYSMGR_FPGAINTF_EMAC0		(1<<2)
> +#define SYSMGR_FPGAINTF_EMAC1		(1<<3)
> +#define SYSMGR_FPGAINTF_NAND		(1<<4)
> +#define SYSMGR_FPGAINTF_SDMMC		(1<<5)
> +
> +/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum                       

There's way too many spaces at the end, past ::enum .

> */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003

[...]

> +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK    0x00000002
> +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK    0x00000002

You're mixing spaces and TABs just past the MSK part.

> +#define SYSMGR_A10_SDMMC_CTRL_SET(smplsel, drvsel)	\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 4) & 0x70))
> +
> +#endif /* _SOCFPGA_SYSTEM_MANAGER_A10_H_ */

[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

[Dinh Nguyen]

On 12/01/2015 12:46 PM, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 05:48:31 PM, dinguyen at opensource.altera.com 
> wrote:
>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>
>> Add system manager defines for Arria10.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
>> ---
>> v2: clean up parenthesis
> 
> [...]
> 
>> +/* bit fields */
>> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		(1<<0)
>> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		(1<<1)
>> +#define SYSMGR_ECC_OCRAM_EN		(1<<0)
>> +#define SYSMGR_ECC_OCRAM_SERR		(1<<3)
>> +#define SYSMGR_ECC_OCRAM_DERR		(1<<4)
> 
> Uh, so you have SYSMGR_FPGAINTF_USEFPGA and _SPIM0 here, which use the same
> bit. How is this supposed to work ? Is this some specialty of A10 ?
> 

Oops, sorry about that. I didn't clean this up with the idea that
reset_manager_a10.c is going away.

Thanks,
Dinh

[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

[Pavel Machek]

On Tue 2015-12-01 10:48:31, dinguyen at opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add system manager defines for Arria10.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

With whitespace cleaned up:

Acked-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: integrate into a5/c5 reset manager
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 66 ++++++++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              | 47 ++++++++++++++-
 2 files changed, 112 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 666a2ef..ada1e39 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -14,7 +14,44 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+struct socfpga_reset_manager {
+	u32	stat;
+	u32	ramstat;
+	u32	miscstat;
+	u32	ctrl;
+	u32	hdsken;
+	u32	hdskreq;
+	u32	hdskack;
+	u32	counts;
+	u32	mpu_mod_rst;
+	u32	per0_mod_rst;
+	u32	per1_mod_rst;
+	u32	brg_mod_rst;
+	u32	sys_mod_rst;
+	u32	coldmodrst;
+	u32	nrstmodrst;
+	u32	dbgmodrst;
+	u32	mpuwarmmask;
+	u32	per0warmmask;
+	u32	per1warmmask;
+	u32	brgwarmmask;
+	u32	syswarmmask;
+	u32	nrstwarmmask;
+	u32	l3warmmask;
+	u32	tststa;
+	u32	tstscratch;
+	u32	hdsktimeout;
+	u32	hmcintr;
+	u32	hmcintren;
+	u32	hmcintrens;
+	u32	hmcintrenr;
+	u32	hmcgpout;
+	u32	hmcgpin;
+};
+#else
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
@@ -27,6 +64,7 @@ struct socfpga_reset_manager {
 	u32	misc_mod_reset;
 	u32	tstscratch;
 };
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -54,6 +92,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)			\
 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+#else
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -73,6 +138,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..b955d39 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,51 @@ static const struct socfpga_reset_manager *reset_manager_base =
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void socfpga_per_reset(u32 reset, int set)
+{
+	const void *reg;
+
+	if (RSTMGR_BANK(reset) == 0)
+		reg = &reset_manager_base->mpu_mod_rst;
+	else if (RSTMGR_BANK(reset) == 1)
+		reg = &reset_manager_base->per0_mod_rst;
+	else if (RSTMGR_BANK(reset) == 2)
+		reg = &reset_manager_base->per1_mod_rst;
+	else if (RSTMGR_BANK(reset) == 3)
+		reg = &reset_manager_base->brg_mod_rst;
+	else if (RSTMGR_BANK(reset) == 4)
+		reg = &reset_manager_base->sys_mod_rst;
+	else    /* Invalid reset register, do nothing */
+		return;
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Disable all the peripherals except L4 watchdog0 and L4 Timer 0.
+ */
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void)
+{
+	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
+			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+
+	unsigned mask_ecc_ocp = 0x0000FF00;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(~l4wd0, &reset_manager_base->per1_mod_rst);
+	setbits_le32(&reset_manager_base->per0_mod_rst, ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(&reset_manager_base->per0_mod_rst, mask_ecc_ocp);
+}
+#else
 void socfpga_per_reset(u32 reset, int set)
 {
 	const void *reg;
@@ -118,3 +162,4 @@ void socfpga_bridges_reset(int enable)
 	}
 }
 #endif
+#endif
-- 
2.6.2

[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:32 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the defines for the reset manager and some basic reset functionality.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: integrate into a5/c5 reset manager

[...]

Hi!

> diff --git a/arch/arm/mach-socfpga/reset_manager.c
> b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..b955d39 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager.c
> @@ -18,7 +18,51 @@ static const struct socfpga_reset_manager
> *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> 
> -/* Assert or de-assert SoCFPGA reset manager reset. */
> +/*
> + * Assert or de-assert SoCFPGA reset manager reset.
> + */
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +void socfpga_per_reset(u32 reset, int set)
> +{
> +	const void *reg;

OK, Dinh, come on. I know you _can_ do better than this crap.

> +	if (RSTMGR_BANK(reset) == 0)
> +		reg = &reset_manager_base->mpu_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 1)
> +		reg = &reset_manager_base->per0_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 2)
> +		reg = &reset_manager_base->per1_mod_rst;

The only difference between gen5 and gen10 in this function is the register 
naming. On gen5, these two registers are called per_mod_rst and per2_mod_rst,
while on gen10, they are called per0_mod_rst and per1_mod_rst . Do you really
think such a trivial change justifies introducing a whole new copy of this
function ?

> +	else if (RSTMGR_BANK(reset) == 3)
> +		reg = &reset_manager_base->brg_mod_rst;
> +	else if (RSTMGR_BANK(reset) == 4)
> +		reg = &reset_manager_base->sys_mod_rst;
> +	else    /* Invalid reset register, do nothing */
> +		return;
> +
> +	if (set)
> +		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> +	else
> +		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> +}
> +
> +/*
> + * Disable all the peripherals except L4 watchdog0 and L4 Timer 0.
> + */
> +void reset_assert_all_peripherals_except_l4wd0_l4timer0(void)
> +{
> +	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
> +			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> +
> +	unsigned mask_ecc_ocp = 0x0000FF00;
> +
> +	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> +	writel(~l4wd0, &reset_manager_base->per1_mod_rst);
> +	setbits_le32(&reset_manager_base->per0_mod_rst, ~mask_ecc_ocp);
> +
> +	/* Finally disable the ECC_OCP */
> +	setbits_le32(&reset_manager_base->per0_mod_rst, mask_ecc_ocp);
> +}
> +#else
>  void socfpga_per_reset(u32 reset, int set)
>  {
>  	const void *reg;
> @@ -118,3 +162,4 @@ void socfpga_bridges_reset(int enable)
>  	}
>  }
>  #endif
> +#endif

[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

[Pavel Machek]

On Tue 2015-12-01 19:51:39, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 05:48:32 PM, dinguyen at opensource.altera.com 
> wrote:
> > From: Dinh Nguyen <dinguyen@opensource.altera.com>
> > 
> > Add the defines for the reset manager and some basic reset functionality.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> > ---
> > v2: integrate into a5/c5 reset manager
> 
> [...]
> 
> Hi!
> 
> > diff --git a/arch/arm/mach-socfpga/reset_manager.c
> > b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..b955d39 100644
> > --- a/arch/arm/mach-socfpga/reset_manager.c
> > +++ b/arch/arm/mach-socfpga/reset_manager.c
> > @@ -18,7 +18,51 @@ static const struct socfpga_reset_manager
> > *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs =
> >  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > 
> > -/* Assert or de-assert SoCFPGA reset manager reset. */
> > +/*
> > + * Assert or de-assert SoCFPGA reset manager reset.
> > + */
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +void socfpga_per_reset(u32 reset, int set)
> > +{
> > +	const void *reg;
> 
> OK, Dinh, come on. I know you _can_ do better than this crap.

Umm. Take a look. We already have that code in tree :-).

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv2 3/9] arm: socfpga: arria10: add sdram defines for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Remove union bitfields
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +++++++++++++++++++++++++
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 0000000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_SOCFPGA_SDRAM_A10_H_
+#define	_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+	u32 ip_rev_id;
+	u32 _pad_0x4_0x7;
+	u32 ddrioctrl;
+	u32 ddrcalstat;
+	u32 mpr_0beat1;
+	u32 mpr_1beat1;
+	u32 mpr_2beat1;
+	u32 mpr_3beat1;
+	u32 mpr_4beat1;
+	u32 mpr_5beat1;
+	u32 mpr_6beat1;
+	u32 mpr_7beat1;
+	u32 mpr_8beat1;
+	u32 mpr_0beat2;
+	u32 mpr_1beat2;
+	u32 mpr_2beat2;
+	u32 mpr_3beat2;
+	u32 mpr_4beat2;
+	u32 mpr_5beat2;
+	u32 mpr_6beat2;
+	u32 mpr_7beat2;
+	u32 mpr_8beat2;
+	u32 _pad_0x58_0x5f[2];
+	u32 auto_precharge;
+	u32 _pad_0x64_0xff[39];
+	u32 eccctrl;
+	u32 eccctrl2;
+	u32 _pad_0x108_0x10f[2];
+	u32 errinten;
+	u32 errintens;
+	u32 errintenr;
+	u32 intmode;
+	u32 intstat;
+	u32 diaginttest;
+	u32 modstat;
+	u32 derraddra;
+	u32 serraddra;
+	u32 _pad_0x134_0x137;
+	u32 autowb_corraddr;
+	u32 serrcntreg;
+	u32 autowb_drop_cntreg;
+	u32 _pad_0x144_0x147;
+	u32 ecc_reg2wreccdatabus;
+	u32 ecc_rdeccdata2regbus;
+	u32 ecc_reg2rdeccdatabus;
+	u32 _pad_0x154_0x15f[3];
+	u32 ecc_diagon;
+	u32 ecc_decstat;
+	u32 _pad_0x168_0x16f[2];
+	u32 ecc_errgenaddr_0;
+	u32 ecc_errgenaddr_1;
+	u32 ecc_errgenaddr_2;
+	u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+	u32 ddr_t_main_scheduler_id_coreid;
+	u32 ddr_t_main_scheduler_id_revisionid;
+	u32 ddr_t_main_scheduler_ddrconf;
+	u32 ddr_t_main_scheduler_ddrtiming;
+	u32 ddr_t_main_scheduler_ddrmode;
+	u32 ddr_t_main_scheduler_readlatency;
+	u32 _pad_0x20_0x34[8];
+	u32 ddr_t_main_scheduler_activate;
+	u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 region0;
+	u32 region1;
+	u32 region2;
+	u32 region3;
+	u32 region4;
+	u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 _pad_0xc_0xf;
+	u32 mpuregion0addr;
+	u32 mpuregion1addr;
+	u32 mpuregion2addr;
+	u32 mpuregion3addr;
+	u32 fpga2sdram0region0addr;
+	u32 fpga2sdram0region1addr;
+	u32 fpga2sdram0region2addr;
+	u32 fpga2sdram0region3addr;
+	u32 fpga2sdram1region0addr;
+	u32 fpga2sdram1region1addr;
+	u32 fpga2sdram1region2addr;
+	u32 fpga2sdram1region3addr;
+	u32 fpga2sdram2region0addr;
+	u32 fpga2sdram2region1addr;
+	u32 fpga2sdram2region2addr;
+	u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 hpsregion0addr;
+	u32 hpsregion1addr;
+	u32 hpsregion2addr;
+	u32 hpsregion3addr;
+	u32 hpsregion4addr;
+	u32 hpsregion5addr;
+	u32 hpsregion6addr;
+	u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+	u32 dbgcfg0;
+	u32 dbgcfg1;
+	u32 dbgcfg2;
+	u32 dbgcfg3;
+	u32 dbgcfg4;
+	u32 dbgcfg5;
+	u32 dbgcfg6;
+	u32 reserve0;
+	u32 reserve1;
+	u32 reserve2;
+	u32 ctrlcfg0;
+	u32 ctrlcfg1;
+	u32 ctrlcfg2;
+	u32 ctrlcfg3;
+	u32 ctrlcfg4;
+	u32 ctrlcfg5;
+	u32 ctrlcfg6;
+	u32 ctrlcfg7;
+	u32 ctrlcfg8;
+	u32 ctrlcfg9;
+	u32 dramtiming0;
+	u32 dramodt0;
+	u32 dramodt1;
+	u32 sbcfg0;
+	u32 sbcfg1;
+	u32 sbcfg2;
+	u32 sbcfg3;
+	u32 sbcfg4;
+	u32 sbcfg5;
+	u32 sbcfg6;
+	u32 sbcfg7;
+	u32 caltiming0;
+	u32 caltiming1;
+	u32 caltiming2;
+	u32 caltiming3;
+	u32 caltiming4;
+	u32 caltiming5;
+	u32 caltiming6;
+	u32 caltiming7;
+	u32 caltiming8;
+	u32 caltiming9;
+	u32 caltiming10;
+	u32 dramaddrw;
+	u32 sideband0;
+	u32 sideband1;
+	u32 sideband2;
+	u32 sideband3;
+	u32 sideband4;
+	u32 sideband5;
+	u32 sideband6;
+	u32 sideband7;
+	u32 sideband8;
+	u32 sideband9;
+	u32 sideband10;
+	u32 sideband11;
+	u32 sideband12;
+	u32 sideband13;
+	u32 sideband14;
+	u32 sideband15;
+	u32 dramsts;
+	u32 dbgdone;
+	u32 dbgsignals;
+	u32 dbgreset;
+	u32 dbgmatch;
+	u32 counter0mask;
+	u32 counter1mask;
+	u32 counter0match;
+	u32 counter1match;
+	u32 niosreserve0;
+	u32 niosreserve1;
+	u32 niosreserve2;
+};
+#endif /*__ASSEMBLY__*/
+
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT	24
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK		0x00F80000
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT	19
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK		0x0007C000
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT	14
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK	0x00003E00
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT	9
+#define IO48_MMR_CTRLCFG0_AC_POS_MASK			0x00000180
+#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT			7
+#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK		0x00000070
+#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT		4
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK			0x0000000F
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT		0
+
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM		(1 << 30)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM		(1 << 29)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM		(1 << 28)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM		(1 << 27)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM		(1 << 26)
+#define IO48_MMR_CTRLCFG1_DQSTRK_EN			(1 << 25)
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK		0x01F80000
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT		19
+#define IO48_MMR_CTRLCFG1_REORDER_READ			(1 << 18)
+#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA		(1 << 17)
+#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA		(1 << 16)
+#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA		(1 << 15)
+#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA		(1 << 14)
+#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA		(1 << 13)
+#define IO48_MMR_CTRLCFG1_REORDER_DATA			(1 << 12)
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC		(1 << 11)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC		(1 << 10)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC		(1 << 9)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC		(1 << 8)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC		(1 << 7)
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK		0x00000060
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT		5
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK	0x0000001F
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT	0
+
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK		0x3F000000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT	24
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK	0x00FC0000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT	18
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK			0x0003F000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT		12
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT		6
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK		0x0000003F
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT		0
+
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK		0x0003F000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT		12
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT		6
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK			0x0000003F
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT			0
+
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT			6
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK			0x3F000000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT			24
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK		0x00FC0000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT		18
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK		0x0003F000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT	12
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT			6
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK		0xFC000000
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT		26
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK		0x03FC0000
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT		18
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT		6
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK		0x0000003F
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT		0
+
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK		0x000000FF
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT		0
+
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK		0x00070000
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT		16
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK	0x0000C000
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT	14
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK		0x00003C00
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT		10
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK		0x000003E0
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT		5
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK		0x0000001F
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT		0
+
+#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK		0x00000003
+
+#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK	0x00000001
+#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK	0x00000002
+#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK	0x00000001
+#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK	0x00000002
+#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK		0x00010000
+#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK	0x00010000
+#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK		0x00000100
+#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK		0x00000001
+#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK		0x00000100
+#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK		0x00000001
+
+#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE		8
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB	6
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB	12
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB	18
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB	21
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB	26
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB	31
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB	1
+
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB	4
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB	10
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB	2
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB	4
+
+#define ALT_NOC_FW_DDR_END_ADDR_LSB	16
+#define ALT_NOC_FW_DDR_ADDR_MASK	0xFFFF
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK		0x00000001
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK		0x00000002
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK		0x00000004
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK		0x00000008
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK		0x00000010
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK		0x00000020
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK		0x00000040
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK		0x00000080
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK		0x00000001
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK		0x00000002
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK		0x00000004
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK		0x00000008
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK	0x00000010
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK	0x00000020
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK	0x00000040
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK	0x00000080
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK	0x00000100
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK	0x00000200
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK	0x00000400
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK	0x00000800
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK	0x00001000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK	0x00002000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK	0x00004000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK	0x00008000
+
+#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK		0x0000003F
+#endif /* _SOCFPGA_SDRAM_A10_H_ */
-- 
2.6.2

[U-Boot] [PATCHv2 3/9] arm: socfpga: arria10: add sdram defines for Arria10

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:33 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the structures for the SDRAM controller on Arria10.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: Remove union bitfields

Applied, thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
has a firewall protection around the SDRAM and OCRAM. These firewalls
are to be disabled in order for U-Boot to function.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: reuse misc functions from a5/c5
---
 arch/arm/mach-socfpga/misc.c | 56 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index bbd31ef..f8aca55 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include <watchdog.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram_a10.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/nic301.h>
@@ -31,11 +32,16 @@ static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
 	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-static struct nic301_registers *nic301_regs =
-	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+	(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
@@ -218,10 +224,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");
+#else
 	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 	puts("CPU:   Altera SoCFPGA Platform\n");
 	socfpga_fpga_id(1);
 	printf("BOOT:  %s\n", bsel_str[bsel].name);
+#endif
 	return 0;
 }
 #endif
@@ -303,6 +313,47 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/*
+ * This function initializes security policies to be consistent across
+ * all logic units in the Arria 10.
+ *
+ * The idea is to set all security policies to be normal, nonsecure
+ * for all units.
+ */
+static void initialize_security_policies(void)
+{
+	/* Put OCRAM in non-secure */
+	writel(0x003f0000, &noc_fw_ocram_base->region0);
+	writel(0x1, &noc_fw_ocram_base->enable);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
+	writel(0x1, &noc_fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+	initialize_security_policies();
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+
+	/* assert reset to all except L4WD0 and L4TIMER0 */
+	reset_assert_all_peripherals_except_l4wd0_l4timer0();
+
+	/* configuring the clock based on handoff */
+	/* TODO: Add call to cm_basic_init() */
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
+	return 0;
+}
+
+#else
+
+static struct nic301_registers *nic301_regs =
+	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -430,3 +481,4 @@ U_BOOT_CMD(
 	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 	""
 );
+#endif
-- 
2.6.2

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:34 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
> overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
> has a firewall protection around the SDRAM and OCRAM. These firewalls
> are to be disabled in order for U-Boot to function.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: reuse misc functions from a5/c5
> ---
>  arch/arm/mach-socfpga/misc.c | 56
> ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54
> insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index bbd31ef..f8aca55 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -15,6 +15,7 @@
>  #include <watchdog.h>
>  #include <asm/arch/reset_manager.h>
>  #include <asm/arch/scan_manager.h>
> +#include <asm/arch/sdram_a10.h>
>  #include <asm/arch/system_manager.h>
>  #include <asm/arch/dwmmc.h>
>  #include <asm/arch/nic301.h>
> @@ -31,11 +32,16 @@ static struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  static struct socfpga_reset_manager *reset_manager_base =
>  	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> -static struct nic301_registers *nic301_regs =
> -	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

For the sake of consistency, I'd just ifdef this with ifdef CV || AV and
the socfpga_noc stuff with ifdef A10 instead of moving things around this
way.

>  static struct scu_registers *scu_regs =
>  	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> 
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
> +	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
> +	(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +#endif
> +
>  int dram_init(void)
>  {
>  	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> @@ -218,10 +224,14 @@ static int socfpga_fpga_id(const bool print_id)
>  #if defined(CONFIG_DISPLAY_CPUINFO)
>  int print_cpuinfo(void)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +	puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");

No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10 platform",
CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?

> +#else
>  	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
>  	puts("CPU:   Altera SoCFPGA Platform\n");
>  	socfpga_fpga_id(1);
>  	printf("BOOT:  %s\n", bsel_str[bsel].name);
> +#endif
>  	return 0;
>  }
>  #endif
> @@ -303,6 +313,47 @@ int arch_cpu_init(void)
>  	return 0;
>  }
> 
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +/*
> + * This function initializes security policies to be consistent across
> + * all logic units in the Arria 10.
> + *
> + * The idea is to set all security policies to be normal, nonsecure
> + * for all units.
> + */
> +static void initialize_security_policies(void)
> +{
> +	/* Put OCRAM in non-secure */
> +	writel(0x003f0000, &noc_fw_ocram_base->region0);
> +	writel(0x1, &noc_fw_ocram_base->enable);
> +
> +	/* Put DDR in non-secure */
> +	writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
> +	writel(0x1, &noc_fw_ddr_l3_base->enable);
> +}
> +
> +int arch_early_init_r(void)
> +{
> +	initialize_security_policies();
> +
> +	/* Configure the L2 controller to make SDRAM start at 0 */
> +	writel(0x1, &pl310->pl310_addr_filter_start);
> +
> +	/* assert reset to all except L4WD0 and L4TIMER0 */
> +	reset_assert_all_peripherals_except_l4wd0_l4timer0();
> +
> +	/* configuring the clock based on handoff */
> +	/* TODO: Add call to cm_basic_init() */
> +
> +	/* Add device descriptor to FPGA device table */
> +	socfpga_fpga_add();
> +	return 0;
> +}
> +
> +#else
> +
> +static struct nic301_registers *nic301_regs =
> +	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>  /*
>   * Convert all NIC-301 AMBA slaves from secure to non-secure
>   */
> @@ -430,3 +481,4 @@ U_BOOT_CMD(
>  	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA
> bridges\n" ""
>  );
> +#endif

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Dinh Nguyen]

On Tue, Dec 1, 2015 at 12:56 PM, Marek Vasut <marex@denx.de> wrote:
> On Tuesday, December 01, 2015 at 05:48:34 PM, dinguyen at opensource.altera.com
> wrote:
>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>
>> Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
>> overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
>> has a firewall protection around the SDRAM and OCRAM. These firewalls
>> are to be disabled in order for U-Boot to function.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
>> ---
>> v2: reuse misc functions from a5/c5
>> ---
>>  arch/arm/mach-socfpga/misc.c | 56
>> ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54
>> insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index bbd31ef..f8aca55 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -15,6 +15,7 @@
>>  #include <watchdog.h>
>>  #include <asm/arch/reset_manager.h>
>>  #include <asm/arch/scan_manager.h>
>> +#include <asm/arch/sdram_a10.h>
>>  #include <asm/arch/system_manager.h>
>>  #include <asm/arch/dwmmc.h>
>>  #include <asm/arch/nic301.h>
>> @@ -31,11 +32,16 @@ static struct socfpga_system_manager *sysmgr_regs =
>>       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>  static struct socfpga_reset_manager *reset_manager_base =
>>       (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
>> -static struct nic301_registers *nic301_regs =
>> -     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>
> For the sake of consistency, I'd just ifdef this with ifdef CV || AV and
> the socfpga_noc stuff with ifdef A10 instead of moving things around this
> way.
>
>>  static struct scu_registers *scu_regs =
>>       (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>>
>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
>> +     (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
>> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
>> +     (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
>> +#endif
>> +
>>  int dram_init(void)
>>  {
>>       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
>> @@ -218,10 +224,14 @@ static int socfpga_fpga_id(const bool print_id)
>>  #if defined(CONFIG_DISPLAY_CPUINFO)
>>  int print_cpuinfo(void)
>>  {
>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +     puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");
>
> No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10 platform",
> CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?
>

The FPGA detection is probably going to be a bit different, so I'm
just not going to
include it for now.

Dinh

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Marek Vasut]

On Wednesday, December 02, 2015 at 06:29:26 AM, Dinh Nguyen wrote:
> On Tue, Dec 1, 2015 at 12:56 PM, Marek Vasut <marex@denx.de> wrote:
> > On Tuesday, December 01, 2015 at 05:48:34 PM,
> > dinguyen at opensource.altera.com
> > 
> > wrote:
> >> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> >> 
> >> Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
> >> overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
> >> has a firewall protection around the SDRAM and OCRAM. These firewalls
> >> are to be disabled in order for U-Boot to function.
> >> 
> >> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> >> ---
> >> v2: reuse misc functions from a5/c5
> >> ---
> >> 
> >>  arch/arm/mach-socfpga/misc.c | 56
> >> 
> >> ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54
> >> insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> >> index bbd31ef..f8aca55 100644
> >> --- a/arch/arm/mach-socfpga/misc.c
> >> +++ b/arch/arm/mach-socfpga/misc.c
> >> @@ -15,6 +15,7 @@
> >> 
> >>  #include <watchdog.h>
> >>  #include <asm/arch/reset_manager.h>
> >>  #include <asm/arch/scan_manager.h>
> >> 
> >> +#include <asm/arch/sdram_a10.h>
> >> 
> >>  #include <asm/arch/system_manager.h>
> >>  #include <asm/arch/dwmmc.h>
> >>  #include <asm/arch/nic301.h>
> >> 
> >> @@ -31,11 +32,16 @@ static struct socfpga_system_manager *sysmgr_regs =
> >> 
> >>       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >>  
> >>  static struct socfpga_reset_manager *reset_manager_base =
> >>  
> >>       (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> >> 
> >> -static struct nic301_registers *nic301_regs =
> >> -     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > 
> > For the sake of consistency, I'd just ifdef this with ifdef CV || AV and
> > the socfpga_noc stuff with ifdef A10 instead of moving things around this
> > way.
> > 
> >>  static struct scu_registers *scu_regs =
> >>  
> >>       (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> >> 
> >> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
> >> +     (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
> >> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
> >> +     (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> >> +#endif
> >> +
> >> 
> >>  int dram_init(void)
> >>  {
> >>  
> >>       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
> >>       PHYS_SDRAM_1_SIZE);
> >> 
> >> @@ -218,10 +224,14 @@ static int socfpga_fpga_id(const bool print_id)
> >> 
> >>  #if defined(CONFIG_DISPLAY_CPUINFO)
> >>  int print_cpuinfo(void)
> >>  {
> >> 
> >> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >> +     puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");
> > 
> > No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> > platform", CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria
> > 10 , right ?
> 
> The FPGA detection is probably going to be a bit different, so I'm
> just not going to
> include it for now.

OK, thanks!

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Pavel Machek]

> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +	puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");
> 
> No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10 platform",
> CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?
>

Well. .. cpu is "generic ARM embedded in SoCFPGA". Maybe replace
"CPU:" with "SoC:"?
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCHv2 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Marek Vasut]

On Thursday, December 03, 2015 at 07:35:54 PM, Pavel Machek wrote:
> > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > +	puts("CPU   : Altera SOCFPGA Arria 10 Platform\n");
> > 
> > No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10
> > platform", CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria
> > 10 , right ?
> 
> Well. .. cpu is "generic ARM embedded in SoCFPGA". Maybe replace
> "CPU:" with "SoC:"?

You don't want that for the sake of consistency with other platforms.

Best regards,
Marek Vasut

[U-Boot] [PATCHv2 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
---
 include/configs/socfpga_arria10_socdk.h | 157 ++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..c1a5b4a
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,157 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_PING
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x8000
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * Environment setup
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Can't poll in semihosting; so turn off automatic boot command
+ */
+#define CONFIG_BOOTCOMMAND "run callscript; run mmcload;" \
+	"run set_initswstate; run mmcboot"
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE		0x2000000
+
+/*
+ * network support
+ */
+#define CONFIG_DESIGNWARE_ETH
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+/* phy */
+#define CONFIG_EPHY0_PHY_ADDR		7
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif	/* CONFIG_DESIGNWARE_ETH */
+
+
+/*
+ * MMC support
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0/* device 0 */
+#define CONFIG_ENV_OFFSET		512/* just after the MBR */
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+/* Enable FAT write support */
+#define CONFIG_FAT_WRITE
+
+/* configure a clustsize smaller than the default 64k */
+#define CONFIG_FS_FAT_MAX_CLUSTSIZE 16384
+/* MMC support */
+#define CONFIG_SDMMC_BASE		(SOCFPGA_SDMMC_ADDRESS)
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL     3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL     0
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SOCFPGA_DWMMC_BUS_HZ	CONFIG_HPS_CLK_SDMMC_HZ
+#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH	4
+/* requird for dw_mmc driver */
+#define CONFIG_BOUNCE_BUFFER
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif /* CONFIG_MMC */
+
+/*
+ * NAND
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_REGS_BASE	0xff200000
+#define CONFIG_SYS_NAND_DATA_BASE	0xff300000
+#define CONFIG_SYS_NAND_BASE		0xff400000
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* The ECC size which either 512 or 1024 */
+#define CONFIG_NAND_DENALI_ECC_SIZE			(512)
+#endif /* CONFIG_NAND_DENALI */
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+#endif	/* __CONFIG_H */
-- 
2.6.2

[U-Boot] [PATCHv2 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:35 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add config for the Arria10 SoC Development Kit.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
> ---
>  include/configs/socfpga_arria10_socdk.h | 157
> ++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+)
>  create mode 100644 include/configs/socfpga_arria10_socdk.h
> 
> diff --git a/include/configs/socfpga_arria10_socdk.h
> b/include/configs/socfpga_arria10_socdk.h new file mode 100644
> index 0000000..c1a5b4a
> --- /dev/null
> +++ b/include/configs/socfpga_arria10_socdk.h
> @@ -0,0 +1,157 @@
> +/*
> + *  Copyright (C) 2015 Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
> +#define __CONFIG_SOCFGPA_ARRIA10_H__
> +
> +#include <asm/arch/base_addr_a10.h>
> +/* U-Boot Commands */
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_FAT_WRITE
> +#define CONFIG_HW_WATCHDOG
> +
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_EXT4
> +#define CONFIG_CMD_EXT4_WRITE
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_FS_GENERIC
> +#define CONFIG_CMD_GPIO
> +#define CONFIG_CMD_GREPENV
> +#define CONFIG_CMD_PING
> +
> +/* Default load address */
> +#define CONFIG_SYS_LOAD_ADDR		0x8000
> +
> +/*
> + * Display CPU and Board Info
> + */
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_DISPLAY_BOARDINFO_LATE
> +
> +/*
> + * Environment setup
> + */
> +#define CONFIG_BOOTDELAY		3
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

Please drop this stuff, it's not necessary. Keep the defaults.

> +/*
> + * Can't poll in semihosting; so turn off automatic boot command
> + */
> +#define CONFIG_BOOTCOMMAND "run callscript; run mmcload;" \
> +	"run set_initswstate; run mmcboot"
> +
> +/*
> + * arguments passed to the bootz command. The value of
> + * CONFIG_BOOTARGS goes into the environment value "bootargs".
> + * Do note the value will overide also the chosen node in FDT blob.
> + */
> +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"verify=n\0" \
> +	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> +	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
> +		"bootm ${loadaddr} - ${fdt_addr}\0" \
> +	"bootimage=zImage\0" \
> +	"fdt_addr=100\0" \
> +	"fdtimage=socfpga.dtb\0" \
> +		"fsloadcmd=ext2load\0" \
> +	"bootm ${loadaddr} - ${fdt_addr}\0" \
> +	"mmcroot=/dev/mmcblk0p2\0" \
> +	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> +		" root=${mmcroot} rw rootwait;" \
> +		"bootz ${loadaddr} - ${fdt_addr}\0" \
> +	"mmcload=mmc rescan;" \
> +		"load mmc 0:1 ${loadaddr} ${bootimage};" \
> +		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> +	"qspiroot=/dev/mtdblock0\0" \
> +	"qspirootfstype=jffs2\0" \
> +	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
> +		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
> +		"bootm ${loadaddr} - ${fdt_addr}\0"
> +
> +/*
> + * Memory configurations
> + */
> +#define PHYS_SDRAM_1_SIZE		0x2000000
> +
> +/*
> + * network support
> + */
> +#define CONFIG_DESIGNWARE_ETH
> +#ifdef CONFIG_DESIGNWARE_ETH
> +#define CONFIG_NET_MULTI

NET_MULTI is long gone.

> +#define CONFIG_DW_ALTDESCRIPTOR

This is enabled in configs/socfpga_* for a few months now.

> +#define CONFIG_DW_SEARCH_PHY
> +#define CONFIG_PHY_GIGE
> +#define CONFIG_DW_AUTONEG
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +/* phy */
> +#define CONFIG_EPHY0_PHY_ADDR		7
> +#define CONFIG_PHY_MICREL
> +#define CONFIG_PHY_MICREL_KSZ9031
> +#endif	/* CONFIG_DESIGNWARE_ETH */

Please just align this with the rest of the boards, also put whatever
hardware configuration _before_ the extra env.

> +/*
> + * MMC support
> + */
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_MMC
> +
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV		0/* device 0 */
> +#define CONFIG_ENV_OFFSET		512/* just after the MBR */
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_MMC
> +/* Enable FAT write support */
> +#define CONFIG_FAT_WRITE
> +
> +/* configure a clustsize smaller than the default 64k */
> +#define CONFIG_FS_FAT_MAX_CLUSTSIZE 16384

What? Why do you have this stuff here ?

> +/* MMC support */
> +#define CONFIG_SDMMC_BASE		(SOCFPGA_SDMMC_ADDRESS)
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_DWMMC
> +#define CONFIG_SOCFPGA_DWMMC
> +#define CONFIG_SOCFPGA_DWMMC_DRVSEL     3
> +#define CONFIG_SOCFPGA_DWMMC_SMPSEL     0
> +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
> +/* using smaller max blk cnt to avoid flooding the limited stack we have
> */ +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ	CONFIG_HPS_CLK_SDMMC_HZ
> +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH	4
> +/* requird for dw_mmc driver */
> +#define CONFIG_BOUNCE_BUFFER
> +#else
> +#define CONFIG_ENV_IS_NOWHERE
> +#endif /* CONFIG_MMC */

Please weed out all the duplicate macros.

> +/*
> + * NAND
> + */
> +#ifdef CONFIG_NAND_DENALI
> +#define CONFIG_CMD_NAND
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_REGS_BASE	0xff200000
> +#define CONFIG_SYS_NAND_DATA_BASE	0xff300000
> +#define CONFIG_SYS_NAND_BASE		0xff400000
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +/* The ECC size which either 512 or 1024 */
> +#define CONFIG_NAND_DENALI_ECC_SIZE			(512)

Drop the parenthesis please.

> +#endif /* CONFIG_NAND_DENALI */

Better part of this goes into socfpga_common.h

> +/* The rest of the configuration is shared */
> +#include <configs/socfpga_common.h>
> +#endif	/* __CONFIG_H */

[U-Boot] [PATCHv2 6/9] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Cleaned up copyright
---
 board/altera/arria10-socdk/Kconfig   | 18 ++++++++++++++++++
 board/altera/arria10-socdk/Makefile  |  7 +++++++
 board/altera/arria10-socdk/socfpga.c | 24 ++++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 0000000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "socfpga_arria10"
+
+config SYS_VENDOR
+	default "altera"
+
+config SYS_SOC
+	default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+	default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 0000000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 0000000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
-- 
2.6.2

[U-Boot] [PATCHv2 6/9] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:36 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add minimal support for the Arria10 SoCDK.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Applied, thanks.

Best regards,
Marek Vasut

[U-Boot] [PATCHv2 7/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: none
---
 configs/socfpga_arria10_defconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..22722a9
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
-- 
2.6.2

[U-Boot] [PATCHv2 7/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:37 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add a defconfig file for Arria10, which does not include enabling SPL.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Please align this with u-boot-socfpga/master, in particular enable CONFIG_DM_MMC 
so MMC gets probed from OF. Also, I cannot pick it until the rest of a10 is 
fleshout out, but I am collecting the a10 patches into u-boot-socfpga/a10 branch 
.

Best regards,
Marek Vasut

[U-Boot] [PATCHv2 8/9] arm: socfpga: arria10: add config option build for arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: none
---
 arch/arm/Kconfig              |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ab0254..1d78e40 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -499,9 +499,9 @@ config RMOBILE
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL
+	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
-	select SPL_OF_CONTROL
+	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SPI_FLASH
 	select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4..82d69ec 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,8 @@
 if ARCH_SOCFPGA
 
+config TARGET_SOCFPGA_ARRIA10
+	bool
+
 config TARGET_SOCFPGA_ARRIA5
 	bool
 
@@ -18,6 +21,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+	bool "Altera SOCFPGA SoCDK (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -34,6 +41,7 @@ endchoice
 
 config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
@@ -41,6 +49,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -51,6 +60,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
-- 
2.6.2

[U-Boot] [PATCHv2 9/9] arm: socfpga: remove building scan manager

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/Makefile | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 316b326..d4c5a42 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,11 +8,14 @@
 #
 
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-	   fpga_manager.o scan_manager.o
+	   fpga_manager.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
+ifneq ($(CONFIG_TARGET_SOCFPGA_ARRIA10),y)
 # QTS-generated config file wrappers
-obj-y	+= wrap_pll_config.o
+obj-y	+= scan_manager.o wrap_pll_config.o
+endif
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
 			   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-- 
2.6.2

[U-Boot] [PATCHv2 9/9] arm: socfpga: remove building scan manager

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:39 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> The scan manager is not needed for the Arria10. Edit the makefile to
> build the scan manager for arria5 and cyclone5 only.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
>  arch/arm/mach-socfpga/Makefile | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/Makefile
> b/arch/arm/mach-socfpga/Makefile index 316b326..d4c5a42 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -8,11 +8,14 @@
>  #
> 
>  obj-y	+= misc.o timer.o reset_manager.o system_manager.o 
clock_manager.o \
> -	   fpga_manager.o scan_manager.o
> +	   fpga_manager.o
> +
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> 
> +ifneq ($(CONFIG_TARGET_SOCFPGA_ARRIA10),y)
>  # QTS-generated config file wrappers
> -obj-y	+= wrap_pll_config.o
> +obj-y	+= scan_manager.o wrap_pll_config.o
> +endif
>  obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
>  			   wrap_sdram_config.o
>  CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)

I'd suggest to use this construct here:

obj-$(CONFIG_TARGET_SOCFPGA_CYCLONE5) += foo.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA5) += foo.o

Best regards,
Marek Vasut