[U-Boot] [PATCHv4 3/9] arm: socfpga: arria10: add reset manager for Arria10

[Pavel Machek <pavel@denx.de>]

On Wed 2015-12-02 13:31:27, dinguyen at opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the defines for the reset manager and some basic reset functionality.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v4: rename mod_reset names to be used by both gen5 and a10
> v3: remove duplicate reset function
>     use CONFIG_SOCFPGA_GEN5
> v2: integrate into a5/c5 reset manager
> ---
>  arch/arm/mach-socfpga/include/mach/reset_manager.h | 71 +++++++++++++++++++++-
>  arch/arm/mach-socfpga/reset_manager.c              | 36 ++++++++---
>  2 files changed, 97 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index e50fbd8..b34c7c6 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -15,19 +15,56 @@ void socfpga_bridges_reset(int enable);
>  void socfpga_per_reset(u32 reset, int set);
>  void socfpga_per_reset_all(void);
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  struct socfpga_reset_manager {
>  	u32	status;
>  	u32	ctrl;
>  	u32	counts;
>  	u32	padding1;
>  	u32	mpu_mod_reset;
> -	u32	per_mod_reset;
> -	u32	per2_mod_reset;
> +	u32	per0_mod_reset; /* per_mod_reset */
> +	u32	per1_mod_reset; /* per2_mod_reset */
>  	u32	brg_mod_reset;
> -	u32	misc_mod_reset;
> +	u32	sys_mod_reset; /* misc_mod_reset */

Umm. Those comments are really hard to understand. Add "in the
datasheet" at the end so that poor reader has chance to see what is
going on?

Thanks,
								Pavel

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