From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 11 Dec 2015 18:32:22 +0100
Subject: [U-Boot] [PATCH 1/2] spl: dm: Add SPL_DM_SEQ_ALIAS config option
In-Reply-To: <566AEFE0.5010708@xilinx.com>
References: <1449845290-31114-1-git-send-email-nathan@nathanrossi.com>
 <201512111607.56816.marex@denx.de> <566AEFE0.5010708@xilinx.com>
Message-ID: <201512111832.22334.marex@denx.de>
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On Friday, December 11, 2015 at 04:46:40 PM, Michal Simek wrote:
> On 11.12.2015 16:07, Marek Vasut wrote:
> > On Friday, December 11, 2015 at 03:48:09 PM, Nathan Rossi wrote:
> >> The Device Model sequence alias feature is required by some Uclasses.
> >> Instead of disabling the feature for all SPL targets allow it to be
> >> configured.
> >> 
> >> The config option is disabled by default to reduce code size for targets
> >> that are not interested or do not require this feature.
> >> 
> >> Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
> >> Cc: Simon Glass <sjg@chromium.org>
> >> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Marek Vasut <marex@denx.de>
> >> Cc: Michal Simek <michal.simek@xilinx.com>
> >> ---
> >> Based on a small amount of inspection for the Zynq platform, enabling
> >> this config option adds ~1KB of code size.
> >> 
> >> Also on a side note, this might affect the socfpga target as it forcibly
> >> overrides the #undef from config_uncmd_spl.h in its common header. I
> >> have Cc'd the respective maintainer for this reason.
> > 
> > The fix for SoCFPGA is easy -- enable the SPL_DM_SEQ_ALIAS in
> > configs/socfpga*. It is needed for booting from QSPI NOR.
> 
> That's probably not the best solution. But of course we can use it.
> IRC Stefan had the same problem.

So what is the solution ?

Best regards,
Marek Vasut