[U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

Marek Vasut
2015-12-15T01:15:00Z

On Tuesday, December 15, 2015 at 02:09:42 AM, Chin Liang See wrote:
> On Tue, 2015-12-15 at 01:32 +0100, Marek Vasut wrote:
> > On Monday, December 14, 2015 at 04:22:57 PM, Chin Liang See wrote:
> > > On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote:
> > > > On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang See
>
> > > > wrote:
> [...]
>
> > > Yeah, I can successfully mounted with ubifs :)
> > >
> > > Just that I still have the issue with U-Boot ubifsmount although I
> > > already applied the patch for cache ARMV7. I will take a look into
> > > ubi
> > > code as I suspect its due to eraseblock size issue.
> >
> > Keep looking, good luck.
>
> Yup, will compare the UBI code with the Linux one.
>
> > The armv7 cache issue is more serious than I thought, I am starting
> > to suspect
> > there is some problem with the L3 interconnect, but I cannot put my
> > finger on
> > it yet.
>
> Hmmm... I can try to help.
>
> FYI, I was trying to understand how the code error in cache-cp15 will
> cause the misbehave. One thing I am suspecting it might due to mismatch
> of cache policy for the memory that store the page table and
> translation page walk mechanism. But with your fix, it should be good
> as they are matching now.

I would suggest to move this to the thread below the CPU_V7 patch.

btw. the L2 cache is not enabled on SoCFPGA at all :-( I have a patch to fix
it, but this doesn't help us. I suspect there might be some synchronisation
or timing issue with accesses through the L3 interconnect, which would point
to NIC301 misconfiguration, but that's purely hypothetical. Do you have some
hardware-level or RTL-level/simulation tool to debug such issues at Altera ?

Best regards,
Marek Vasut