From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Thu, 17 Dec 2015 16:40:19 +0100
Subject: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for
	MX6 Q/D/DL
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 <CAJ+vNU1rzi3y4Dc63bE1tP-1MKw1HEtq=7hpqHnJEvHB+yDNFg@mail.gmail.com>
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On Thursday, December 17, 2015 at 04:36:20 PM, Tim Harvey wrote:
> On Wed, Dec 16, 2015 at 6:40 AM, Marek Vasut <marex@denx.de> wrote:
> > Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
> > fine-tunes the behavior of the MMDC controller in order to improve
> > the signal integrity and memory stability.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> 
> Marek,
> 
> This is great - this would be a great addition to U-Boot IMX6 SPL.
> 
> You must have forgotten to post a dependent patch that adds some of
> the registers to mmdc_p_regs. If you can post that I can run this
> through some testing.

What exactly is missing please ? I am using this on Novena for a while
without issues.

> Also, in a follow-on post we should add some
> more verbiage about how long this takes to perform (I believe you told
> me ~10ms) and where to refer in the IMX6 RM's for the steps followed.

Freescale AN4467 is the right thing ... I mean NXP AN4467 of course.

Best regards,
Marek Vasut