From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Sun, 20 Dec 2015 03:56:35 +0100
Subject: [U-Boot] [PATCH] arm: socfpga: Actually enable L2 cache
In-Reply-To: <567614ED.7070104@denx.de>
References: <1450504730-10190-1-git-send-email-marex@denx.de>
 <201512191732.04949.marex@denx.de> <567614ED.7070104@denx.de>
Message-ID: <201512200356.35277.marex@denx.de>
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To: u-boot@lists.denx.de

On Sunday, December 20, 2015 at 03:39:41 AM, Stefan Roese wrote:
> On 19.12.2015 17:32, Marek Vasut wrote:
> > On Saturday, December 19, 2015 at 11:39:34 AM, Stefan Roese wrote:
> >> On 19.12.2015 11:03, Stefan Roese wrote:
> >>> On 19.12.2015 06:58, Marek Vasut wrote:
> >>>> The L2 cache was never enabled in the v7_outer_cache_enable(), fix
> >>>> this and enable the L2 cache.
> >>>> 
> >>>> Signed-off-by: Marek Vasut <marex@denx.de>
> >>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> >>>> Cc: Chin Liang See <clsee@altera.com>
> >>>> ---
> >>>> 
> >>>>    arch/arm/mach-socfpga/misc.c | 7 +++++--
> >>>>    1 file changed, 5 insertions(+), 2 deletions(-)
> >>>> 
> >>>> diff --git a/arch/arm/mach-socfpga/misc.c
> >>>> b/arch/arm/mach-socfpga/misc.c index b110f5b..621f5d9 100644
> >>>> --- a/arch/arm/mach-socfpga/misc.c
> >>>> +++ b/arch/arm/mach-socfpga/misc.c
> >>>> @@ -54,14 +54,17 @@ void enable_caches(void)
> >>>> 
> >>>>    void v7_outer_cache_enable(void)
> >>>>    {
> >>>> 
> >>>> -    /* disable the L2 cache */
> >>>> -    writel(0, &pl310->pl310_ctrl);
> >>>> +    /* Disable the L2 cache */
> >>>> +    clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> >>>> 
> >>>>        /* enable BRESP, instruction and data prefetch, full line of
> >>>> 
> >>>> zeroes */
> >>>> 
> >>>>        setbits_le32(&pl310->pl310_aux_ctrl,
> >>>>        
> >>>>                 L310_AUX_CTRL_DATA_PREFETCH_MASK |
> >>>>                 L310_AUX_CTRL_INST_PREFETCH_MASK |
> >>>>                 L310_SHARED_ATT_OVERRIDE_ENABLE);
> >>>> 
> >>>> +
> >>>> +    /* Enable the L2 cache */
> >>>> +    setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> >>> 
> >>> Thanks Marek. I would be interested in some number here. Do you see
> >>> a bigger change in the performance (ethernet driver or dhrystone)
> >>> by enabling the L2 cache?
> >> 
> >> And another comment. It might be necessary to disable the L2 cache
> >> when booting into Linux by providing the v7_outer_cache_enable()
> >> function. I noticed problems in Linux with MVEBU with the L2
> >> cache still enabled.
> > 
> > This is the v7_outer_cache_enable() function. Do you have anything else
> > in mind ?
> 
> Yes, I meant v7_outer_cache_disable() of course.

Got it, thanks.

Best regards,
Marek Vasut