[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

Marek Vasut
2015-12-23T01:26:55Z

On Wednesday, December 23, 2015 at 02:25:29 AM, ?? ? wrote:
> On Dec 22, 2015, at 05:22 PM, ?? ? <shengjiangwu@icloud.com> wrote:
>
>
>
> On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
>
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
>
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> >
> > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > Cc: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefan Roese <sr@denx.de>
>
> Applied, thanks.
>
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
>
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
>
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
>
>
> Best regards,
> Marek Vasut
>
>
> Hi Marek,
>
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.
>
> Best Regards,
> ShengjiangWu
>
> => reset
> resetting ...
>
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
>
>
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
>
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0 at ff704000: 0
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet at ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot: 0
> => env default -a
> ## Resetting to default environment
> => setenv netmask 255.255.254.0
> => setenv gatewayip 128.224.98.1
> => setenv ipaddr 128.224.98.85
> => setenv serverip 128.224.99.137
> => setenv ethaddr 00:04:9f:13:57:b4
> => saveenv
> Saving Environment to MMC...
> Writing to MMC(0)... done
> => reset
> resetting ...
>
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
>
>
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
>
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0 at ff704000: 0
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net: eth0: ethernet at ff702000
> Hit any key to stop autoboot: 0
> => tftp 0x8000000 /tftpboot/altera/uVxWorks
> Speed: 100, full duplex
> Using ethernet at ff702000 device
> TFTP from server 128.224.99.137; our IP address is 128.224.98.85
> Filename '/tftpboot/altera/uVxWorks'.
> Load address: 0x8000000
> Loading: #################################################################
> #################################################################
> #################################################################
> #################################################################
> #################################################################
> #################################################################
> ################################################
> 3.3 MiB/s
> done
> Bytes transferred = 6418496 (61f040 hex)
> => sf probe
> SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total
> 128 MiB => sf read 0x7000000 0 0x60000
> device 0 offset 0x0, size 0x60000
> SF: 393216 bytes @ 0x0 Read: OK
> => md 0x7000000
> 07000000: ea00001a e59ff014 e59ff014 e59ff014 ................
> 07000010: e59ff014 e59ff014 e59ff014 e59ff014 ................
> 07000020: ffff0020 ffff0024 ffff0028 ffff002c ...$...(...,...
> 07000030: ffff0030 ffff0100 ffff0038 12345678 0.......8...xV4.
> 07000040: 31305341 2e160000 01390000 ea000007 AS01......9.....
> 07000050: 01000040 0000b854 0000b854 0000b900 @...T...T.......
> 07000060: 0000b854 0badc0de 0badc0de 0badc0de T...............
> 07000070: eb000040 e10f0000 e3c0001f e38000d3 @...............
> 07000080: e129f000 ee110f10 e3c00a02 ee010f10 ..).............
> 07000090: e59f00a8 ee0c0f10 eb000008 eb000015 ................
> 070000a0: eb000690 ee070f15 ee070f9a ee070f95 ................
> 070000b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ........../.../.
> 070000c0: e3a00000 ee080f17 ee070f15 ee070fd5 ................
> 070000d0: ee070f9a ee070f95 ee110f10 e3c00a02 ................
> 070000e0: e3c00007 e3800002 e3800b02 e3800a01 ................
> 070000f0: ee010f10 e1a0f00e ea000018 e320f000 .............. .
> =>
>
> BTW, I tested on master branch of u-boot-socfpga, not SoCDK.

Oh yeah, CV socdk is the abbreviation for "cyclone v soc development kit".

btw can you please fix your mailer so it adds ">" before the quoted text?