* [U-Boot] [PATCH V2] arm: socfpga: Actually enable L2 cache
@ 2015-12-20 3:00 Marek Vasut
2015-12-21 9:54 ` Chin Liang See
0 siblings, 1 reply; 3+ messages in thread
From: Marek Vasut @ 2015-12-20 3:00 UTC (permalink / raw)
To: u-boot
The L2 cache was never enabled in the v7_outer_cache_enable(), fix
this and enable the L2 cache.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
V2: Add v7_outer_cache_disable() as suggested by SR .
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index b110f5b..a54d2b9 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,14 +54,23 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
- /* disable the L2 cache */
- writel(0, &pl310->pl310_ctrl);
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [U-Boot] [PATCH V2] arm: socfpga: Actually enable L2 cache
2015-12-20 3:00 [U-Boot] [PATCH V2] arm: socfpga: Actually enable L2 cache Marek Vasut
@ 2015-12-21 9:54 ` Chin Liang See
2015-12-21 14:20 ` Marek Vasut
0 siblings, 1 reply; 3+ messages in thread
From: Chin Liang See @ 2015-12-21 9:54 UTC (permalink / raw)
To: u-boot
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> The L2 cache was never enabled in the v7_outer_cache_enable(), fix
> this and enable the L2 cache.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Chin Liang See <clsee@altera.com>
> ---
> arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> V2: Add v7_outer_cache_disable() as suggested by SR .
>
Acked-by: Chin Liang See <clsee@altera.com>
Thanks
Chin Liang
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH V2] arm: socfpga: Actually enable L2 cache
2015-12-21 9:54 ` Chin Liang See
@ 2015-12-21 14:20 ` Marek Vasut
0 siblings, 0 replies; 3+ messages in thread
From: Marek Vasut @ 2015-12-21 14:20 UTC (permalink / raw)
To: u-boot
On Monday, December 21, 2015 at 10:54:22 AM, Chin Liang See wrote:
> On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> > The L2 cache was never enabled in the v7_outer_cache_enable(), fix
> > this and enable the L2 cache.
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Chin Liang See <clsee@altera.com>
> > ---
> >
> > arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > V2: Add v7_outer_cache_disable() as suggested by SR .
>
> Acked-by: Chin Liang See <clsee@altera.com>
Applied, thanks.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-12-20 3:00 [U-Boot] [PATCH V2] arm: socfpga: Actually enable L2 cache Marek Vasut
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