From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] arm: imx6: Enable DDR calibration on Novena
Date: Tue, 22 Dec 2015 15:56:16 +0100 [thread overview]
Message-ID: <201512221556.16949.marex@denx.de> (raw)
In-Reply-To: <56790A08.2050408@mail.bg>
On Tuesday, December 22, 2015 at 09:30:00 AM, Nikolay Dimitrov wrote:
> Hi Marek,
>
> On 12/22/2015 03:26 AM, Marek Vasut wrote:
> > On Sunday, December 20, 2015 at 08:33:58 PM, Eric Nelson wrote:
> >> Hi Marek,
> >>
> >> On 12/16/2015 07:40 AM, Marek Vasut wrote:
> >>> Enable the DDR calibration functionality on Novena to deal with the
> >>> memory SoDIMM on this board.
> >>
> >> Shouldn't this be in two patches?
> >
> > Not really, the old values work without the enabled calibration. This
> > change needs to be done atomically.
> >
> > [...]
> >
> >>> static void ccgr_init(void)
> >>>
> >>> @@ -601,6 +601,11 @@ void board_init_f(ulong dummy)
> >>>
> >>> mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
> >>> mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib,
> >>> &elpida_4gib_1600);
> >>>
> >>> + /* Perform DDR DRAM calibration */
> >>> + udelay(100);
> >>
> >> Shouldn't the return values be tested?
> >
> > I guess yes, but if the calibration fails, that what ? It's game over ;-)
>
> Do you think it's possible/practical to reboot the system in this case?
Well, you can call hang() , that's how we've been handling critical failures.
Best regards,
Marek Vasut
next prev parent reply other threads:[~2015-12-22 14:56 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-16 14:40 [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL Marek Vasut
2015-12-16 14:40 ` [U-Boot] [PATCH 2/2] arm: imx6: Enable DDR calibration on Novena Marek Vasut
2015-12-20 19:46 ` Eric Nelson
[not found] ` <567702A6.9070107@cox.net>
2015-12-22 1:26 ` Marek Vasut
2015-12-22 8:30 ` Nikolay Dimitrov
2015-12-22 14:56 ` Marek Vasut [this message]
2015-12-16 15:00 ` [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL Eric Nelson
2015-12-16 15:33 ` Marek Vasut
2015-12-16 16:28 ` Eric Nelson
2015-12-16 16:50 ` Marek Vasut
2015-12-16 17:07 ` Eric Nelson
2015-12-16 17:11 ` Marek Vasut
2015-12-17 15:39 ` Tim Harvey
2015-12-17 15:48 ` Eric Nelson
2015-12-17 15:36 ` Tim Harvey
2015-12-17 15:40 ` Marek Vasut
2015-12-17 16:15 ` Tim Harvey
2015-12-17 16:17 ` Marek Vasut
2015-12-17 21:32 ` Nikolay Dimitrov
2015-12-17 22:11 ` Marek Vasut
2015-12-20 19:31 ` Eric Nelson
2015-12-22 1:52 ` Marek Vasut
2015-12-22 15:37 ` Eric Nelson
2016-01-14 2:10 ` Marek Vasut
2016-01-14 2:37 ` Eric Nelson
2016-01-14 2:50 ` Marek Vasut
2016-01-14 2:52 ` Eric Nelson
2016-01-14 3:06 ` Marek Vasut
2016-01-14 14:25 ` Tim Harvey
2016-01-24 10:47 ` Stefano Babic
2016-01-24 16:01 ` Marek Vasut
2016-01-24 17:03 ` Stefano Babic
2016-01-24 17:11 ` Marek Vasut
2016-01-24 17:18 ` Stefano Babic
2016-01-24 17:22 ` Marek Vasut
2016-01-24 19:33 ` Tom Rini
2016-01-24 22:07 ` Marek Vasut
2016-01-24 22:21 ` Tom Rini
2016-01-24 23:00 ` Marek Vasut
2016-01-24 23:30 ` Tom Rini
2016-01-24 23:55 ` Marek Vasut
2016-01-31 17:25 ` Marek Vasut
2016-06-02 13:20 ` Tim Harvey
2016-06-02 14:23 ` Stefano Babic
2016-06-02 15:25 ` Tim Harvey
2015-12-22 4:13 ` Tim Harvey
2015-12-22 14:47 ` Eric Nelson
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