From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Date: Sun, 27 Dec 2015 18:16:07 +0100 Subject: [U-Boot] [linux-sunxi] Re: PSCI for H3 In-Reply-To: <20151223121415.050a3955@i7> References: <564B3A7E.6040800@gmail.com> <20151223121415.050a3955@i7> Message-ID: <20151227171607.GG30359@lukather> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Dec 23, 2015 at 12:14:15PM +0200, Siarhei Siamashka wrote: > On Tue, 17 Nov 2015 15:32:30 +0100 > Jens Kuske wrote: > > > On 16/11/15 07:26, Chen-Yu Tsai wrote: > > > Hi everyone, > > > > > > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that > > > includes Jens' patches. > > > > > > For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs. > > > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to > > > dig through the SDK. > > > > > > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last > > > encountered issues with on the A31s. This controls non-secure access to a whole > > > bunch of peripherals, which we'll need to enable for Linux to run non-secure. > > > > There is also register 0x2f0 in the CCU, it defaults to disabling > > non-secure access to all clock registers. > > > > Jens > > > > How about just enabling SMP on Allwinner H3 in an old unfashionable way > while all these non-secure access limiters are still being under > investigation? I'd really prefer not to. This ends up being dead code that no-one uses, but we can't really remove. Adding support for the H3 support would only delay that removal once again. What controller are you having issues accessing? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: