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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: cache: Implement cache range check for v7
Date: Mon, 28 Dec 2015 16:23:46 +0100	[thread overview]
Message-ID: <201512281623.46851.marex@denx.de> (raw)
In-Reply-To: <201512110536.15139.marex@denx.de>

On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote:
> > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote:
> > > Add code to aid tracking down cache alignment issues.
> > > In case DEBUG is defined in the cache.c, this code will
> > > check alignment of each attempt to flush/invalidate data
> > > cache and print a warning if the alignment is incorrect.
> > > If DEBUG is not defined, this code is optimized out.
> > > 
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > > Cc: Tom Rini <trini@konsulko.com>
> > 
> > Bump ?
> 
> Bump ?

Bump #3 ?

> > >  arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
> > >  1 file changed, 21 insertions(+)
> > > 
> > > diff --git a/arch/arm/cpu/armv7/cache_v7.c
> > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644
> > > --- a/arch/arm/cpu/armv7/cache_v7.c
> > > +++ b/arch/arm/cpu/armv7/cache_v7.c
> > > @@ -16,6 +16,23 @@
> > > 
> > >  #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
> > >  
> > >  #ifndef CONFIG_SYS_DCACHE_OFF
> > > 
> > > +static int check_cache_range(unsigned long start, unsigned long stop)
> > > +{
> > > +	int ok = 1;
> > > +
> > > +	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> > > +		ok = 0;
> > > +
> > > +	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> > > +		ok = 0;
> > > +
> > > +	if (!ok)
> > > +		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
> > > +			start, stop);
> > > +
> > > +	return ok;
> > > +}
> > > +
> > > 
> > >  /*
> > >  
> > >   * Write the level and type you want to Cache Size Selection
> > > 
> > > Register(CSSELR) * to get size details from Current Cache Size ID
> > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)
> > > 
> > >   */
> > >  
> > >  void invalidate_dcache_range(unsigned long start, unsigned long stop)
> > >  {
> > > 
> > > +	check_cache_range(start, stop);
> > > +
> > > 
> > >  	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
> > >  	
> > >  	v7_outer_cache_inval_range(start, stop);
> > > 
> > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,
> > > unsigned long stop) */
> > > 
> > >  void flush_dcache_range(unsigned long start, unsigned long stop)
> > >  {
> > > 
> > > +	check_cache_range(start, stop);
> > > +
> > > 
> > >  	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
> > >  	
> > >  	v7_outer_cache_flush_range(start, stop);
> > 
> > Best regards,
> > Marek Vasut

Best regards,
Marek Vasut

  reply	other threads:[~2015-12-28 15:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-27 20:34 [U-Boot] [PATCH] arm: cache: Implement cache range check for v7 Marek Vasut
2015-08-04 10:12 ` Marek Vasut
2015-12-01 17:23 ` Marek Vasut
2015-12-11  4:36   ` Marek Vasut
2015-12-28 15:23     ` Marek Vasut [this message]
2016-01-24 17:28       ` Marek Vasut
2016-01-25 16:04         ` Tom Rini
2016-01-25 21:22           ` Albert ARIBAUD

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