[U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

Marek Vasut
2015-12-24T15:12:10Z

On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote:

[...]

> >> +LEAF(lowlevel_init)
> >> + /* These three WLAN_RESET will avoid original issue */
> >> + li t3, 0x03
> >> +1:
> >> + li t0, KSEG1ADDR(AR71XX_RESET_BASE)
> >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> + ori t1, t1, 0x0800
> >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> + nop
> >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> + li t2, 0xfffff7ff
> >> + and t1, t1, t2
> >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> + nop
> >> + addi t3, t3, -1
> >> + bnez t3, 1b
> >> + nop
> >
> > This should be also easy to rewrite into C , right ?
>
> C runtime environment is not available.
> C stack is not ready before DDR has initialized.

Just point the stack into a locked cacheline or some onchip RAM and there
you have a C runtime. That should be pretty easy :)

[...]

> >> +phys_size_t initdram(int board_type)
> >> +{
> >> + uint8_t *addr, *p;
> >> + int i;
> >> +
> >> + ddr_tap_init();
> >> + addr = (uint8_t *)KSEG1;
> >> + *addr = 0x77;
> >> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
> >> + p += 0x1000000;
> >> + *p = i;
> >> + if (*addr != 0x77)
> >> + break;
> >> + }
> >
> > What is this and how does it work ?
>
> Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are,
so please explain it to me in a bit more detail.

> >> + return (phys_size_t)(p - addr);
> >> +}
> >

[...]

> >> + if (reg) {
> >> + val = RST_READ(reg);
> >> + val |= AR71XX_RESET_FULL_CHIP;
> >> + RST_WRITE(reg, val);
> >
> > setbits_le32() please.
>
> Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

> Other, I don't think there is better in being so explicit and using
> little-endian.

I believe your register accesses should have correct endianness exactly
beause mips can be both endian.