* [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg
@ 2016-01-04 6:10 Peng Fan
2016-01-04 6:10 ` [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation Peng Fan
2016-01-05 18:21 ` [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Eric Nelson
0 siblings, 2 replies; 6+ messages in thread
From: Peng Fan @ 2016-01-04 6:10 UTC (permalink / raw)
To: u-boot
Add more entries for structure mxc_ccm_reg.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx6/crm_regs.h | 87 ++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 13e0a3d..787eb68 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -103,6 +103,93 @@ struct mxc_ccm_reg {
u32 analog_pfd_528_set;
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
+ u32 reg_1p1;
+ u32 reg_1p1_set;
+ u32 reg_1p1_clr;
+ u32 reg_1p1_tog;
+ u32 reg_3p0;
+ u32 reg_3p0_set;
+ u32 reg_3p0_clr;
+ u32 reg_3p0_tog;
+ u32 reg_2p5;
+ u32 reg_2p5_set;
+ u32 reg_2p5_clr;
+ u32 reg_2p5_tog;
+ u32 reg_core;
+ u32 reg_core_set;
+ u32 reg_core_clr;
+ u32 reg_core_tog;
+ u32 ana_misc0;
+ u32 ana_misc0_set;
+ u32 ana_misc0_clr;
+ u32 ana_misc0_tog;
+ u32 ana_misc1;
+ u32 ana_misc1_set;
+ u32 ana_misc1_clr;
+ u32 ana_misc1_tog;
+ u32 ana_misc2;
+ u32 ana_misc2_set;
+ u32 ana_misc2_clr;
+ u32 ana_misc2_tog;
+ u32 tempsense0;
+ u32 tempsense0_set;
+ u32 tempsense0_clr;
+ u32 tempsense0_tog;
+ u32 tempsense1;
+ u32 tempsense1_set;
+ u32 tempsense1_clr;
+ u32 tempsense1_tog;
+ u32 usb1_vbus_detect;
+ u32 usb1_vbus_detect_set;
+ u32 usb1_vbus_detect_clr;
+ u32 usb1_vbus_detect_tog;
+ u32 usb1_chrg_detect;
+ u32 usb1_chrg_detect_set;
+ u32 usb1_chrg_detect_clr;
+ u32 usb1_chrg_detect_tog;
+ u32 usb1_vbus_det_stat;
+ u32 usb1_vbus_det_stat_set;
+ u32 usb1_vbus_det_stat_clr;
+ u32 usb1_vbus_det_stat_tog;
+ u32 usb1_chrg_det_stat;
+ u32 usb1_chrg_det_stat_set;
+ u32 usb1_chrg_det_stat_clr;
+ u32 usb1_chrg_det_stat_tog;
+ u32 usb1_loopback;
+ u32 usb1_loopback_set;
+ u32 usb1_loopback_clr;
+ u32 usb1_loopback_tog;
+ u32 usb1_misc;
+ u32 usb1_misc_set;
+ u32 usb1_misc_clr;
+ u32 usb1_misc_tog;
+ u32 usb2_vbus_detect;
+ u32 usb2_vbus_detect_set;
+ u32 usb2_vbus_detect_clr;
+ u32 usb2_vbus_detect_tog;
+ u32 usb2_chrg_detect;
+ u32 usb2_chrg_detect_set;
+ u32 usb2_chrg_detect_clr;
+ u32 usb2_chrg_detect_tog;
+ u32 usb2_vbus_det_stat;
+ u32 usb2_vbus_det_stat_set;
+ u32 usb2_vbus_det_stat_clr;
+ u32 usb2_vbus_det_stat_tog;
+ u32 usb2_chrg_det_stat;
+ u32 usb2_chrg_det_stat_set;
+ u32 usb2_chrg_det_stat_clr;
+ u32 usb2_chrg_det_stat_tog;
+ u32 usb2_loopback;
+ u32 usb2_loopback_set;
+ u32 usb2_loopback_clr;
+ u32 usb2_loopback_tog;
+ u32 usb2_misc;
+ u32 usb2_misc_set;
+ u32 usb2_misc_clr;
+ u32 usb2_misc_tog;
+ u32 digprog;
+ u32 reserved1[7];
+ u32 digprog_sololite;
};
#endif
--
2.6.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation
2016-01-04 6:10 [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Peng Fan
@ 2016-01-04 6:10 ` Peng Fan
2016-01-05 19:06 ` Eric Nelson
2016-01-05 18:21 ` [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Eric Nelson
1 sibling, 1 reply; 6+ messages in thread
From: Peng Fan @ 2016-01-04 6:10 UTC (permalink / raw)
To: u-boot
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 63 +++++++++++++++++++++++++++++++++++++++---
1 file changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 64514b1..1506c04 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -18,6 +18,8 @@ enum pll_clocks {
PLL_BUS, /* System Bus PLL*/
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
+ PLL_AUDIO, /* AUDIO PLL */
+ PLL_VIDEO, /* AUDIO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
- u32 div;
+ u32 div, test_div, pll_num, pll_denom;
switch (pll) {
case PLL_SYS:
@@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return 25000000 * (div + (div >> 1) + 1);
+ case PLL_AUDIO:
+ div = __raw_readl(&imx_ccm->analog_pll_audio);
+ if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
+ test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
+ BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
+ case PLL_VIDEO:
+ div = __raw_readl(&imx_ccm->analog_pll_video);
+ if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
+ test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
+ BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
default:
return 0;
}
@@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 freq, podf, per2_clk2_podf;
+ u32 freq, podf, per2_clk2_podf, misc2_audio_div;
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
@@ -472,9 +512,24 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ misc2_audio_div = ((__raw_readl(&imx_ccm->ana_misc2)
+ >> 22) & 2) |
+ ((__raw_readl(&imx_ccm->ana_misc2)
+ >> 15) & 1);
+ switch (misc2_audio_div) {
+ case 0:
+ case 2:
+ misc2_audio_div = 1;
+ break;
+ case 1:
+ misc2_audio_div = 2;
break;
+ case 3:
+ misc2_audio_div = 4;
+ break;
+ }
+ freq = decode_pll(PLL_AUDIO, MXC_HCLK) / misc2_audio_div;
+ break;
}
}
return freq / (podf + 1) / (per2_clk2_podf + 1);
--
2.6.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg
2016-01-04 6:10 [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Peng Fan
2016-01-04 6:10 ` [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation Peng Fan
@ 2016-01-05 18:21 ` Eric Nelson
2016-01-06 1:39 ` Peng Fan
1 sibling, 1 reply; 6+ messages in thread
From: Eric Nelson @ 2016-01-05 18:21 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 01/03/2016 11:10 PM, Peng Fan wrote:
> Add more entries for structure mxc_ccm_reg.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> arch/arm/include/asm/arch-mx6/crm_regs.h | 87 ++++++++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 13e0a3d..787eb68 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -103,6 +103,93 @@ struct mxc_ccm_reg {
> u32 analog_pfd_528_set;
> u32 analog_pfd_528_clr;
> u32 analog_pfd_528_tog;
I'd like to see some comments here about where in the reference manuals
these registers are defined, since they're not in the CCM section.
Also, I think these should be named to match the RM
i.e. pmu_reg_1p1
> + u32 reg_1p1;
> + u32 reg_1p1_set;
> + u32 reg_1p1_clr;
> + u32 reg_1p1_tog;
> + u32 reg_3p0;
> + u32 reg_3p0_set;
> + u32 reg_3p0_clr;
> + u32 reg_3p0_tog;
> + u32 reg_2p5;
> + u32 reg_2p5_set;
> + u32 reg_2p5_clr;
> + u32 reg_2p5_tog;
> + u32 reg_core;
> + u32 reg_core_set;
> + u32 reg_core_clr;
> + u32 reg_core_tog;
> + u32 ana_misc0;
> + u32 ana_misc0_set;
> + u32 ana_misc0_clr;
> + u32 ana_misc0_tog;
> + u32 ana_misc1;
> + u32 ana_misc1_set;
> + u32 ana_misc1_clr;
> + u32 ana_misc1_tog;
> + u32 ana_misc2;
> + u32 ana_misc2_set;
> + u32 ana_misc2_clr;
... pmu_misc2_tog
> + u32 ana_misc2_tog;
TEMPMON registers
> + u32 tempsense0;
> + u32 tempsense0_set;
> + u32 tempsense0_clr;
> + u32 tempsense0_tog;
> + u32 tempsense1;
> + u32 tempsense1_set;
> + u32 tempsense1_clr;
> + u32 tempsense1_tog;
... and USB_ANALOG here
> + u32 usb1_vbus_detect;
> + u32 usb1_vbus_detect_set;
> + u32 usb1_vbus_detect_clr;
> + u32 usb1_vbus_detect_tog;
> + u32 usb1_chrg_detect;
> + u32 usb1_chrg_detect_set;
> + u32 usb1_chrg_detect_clr;
> + u32 usb1_chrg_detect_tog;
> + u32 usb1_vbus_det_stat;
> + u32 usb1_vbus_det_stat_set;
> + u32 usb1_vbus_det_stat_clr;
> + u32 usb1_vbus_det_stat_tog;
> + u32 usb1_chrg_det_stat;
> + u32 usb1_chrg_det_stat_set;
> + u32 usb1_chrg_det_stat_clr;
> + u32 usb1_chrg_det_stat_tog;
> + u32 usb1_loopback;
> + u32 usb1_loopback_set;
> + u32 usb1_loopback_clr;
> + u32 usb1_loopback_tog;
> + u32 usb1_misc;
> + u32 usb1_misc_set;
> + u32 usb1_misc_clr;
> + u32 usb1_misc_tog;
> + u32 usb2_vbus_detect;
> + u32 usb2_vbus_detect_set;
> + u32 usb2_vbus_detect_clr;
> + u32 usb2_vbus_detect_tog;
> + u32 usb2_chrg_detect;
> + u32 usb2_chrg_detect_set;
> + u32 usb2_chrg_detect_clr;
> + u32 usb2_chrg_detect_tog;
> + u32 usb2_vbus_det_stat;
> + u32 usb2_vbus_det_stat_set;
> + u32 usb2_vbus_det_stat_clr;
> + u32 usb2_vbus_det_stat_tog;
> + u32 usb2_chrg_det_stat;
> + u32 usb2_chrg_det_stat_set;
> + u32 usb2_chrg_det_stat_clr;
> + u32 usb2_chrg_det_stat_tog;
> + u32 usb2_loopback;
> + u32 usb2_loopback_set;
> + u32 usb2_loopback_clr;
> + u32 usb2_loopback_tog;
> + u32 usb2_misc;
> + u32 usb2_misc_set;
> + u32 usb2_misc_clr;
> + u32 usb2_misc_tog;
> + u32 digprog;
> + u32 reserved1[7];
> + u32 digprog_sololite;
> };
> #endif
>
>
Otherwise, I checked these against the i.MX6DQ/SDL/SL and UL manuals
(not i.MX6SX), and
Reviewed-By: Eric Nelson <eric@nelint.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation
2016-01-04 6:10 ` [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation Peng Fan
@ 2016-01-05 19:06 ` Eric Nelson
2016-01-06 1:47 ` Peng Fan
0 siblings, 1 reply; 6+ messages in thread
From: Eric Nelson @ 2016-01-05 19:06 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 01/03/2016 11:10 PM, Peng Fan wrote:
> Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
> Processor Reference Manual and "Figure 18-5. BUS clock generation" of
> i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
> sources from pll4_main_clk(pll_audio), the calculation is wrong.
>
> Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
> for decode_pll.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> arch/arm/cpu/armv7/mx6/clock.c | 63 +++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 59 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index 64514b1..1506c04 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -18,6 +18,8 @@ enum pll_clocks {
> PLL_BUS, /* System Bus PLL*/
> PLL_USBOTG, /* OTG USB PLL */
> PLL_ENET, /* ENET PLL */
> + PLL_AUDIO, /* AUDIO PLL */
> + PLL_VIDEO, /* AUDIO PLL */
> };
>
> struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> @@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
> }
> static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> {
> - u32 div;
> + u32 div, test_div, pll_num, pll_denom;
>
> switch (pll) {
> case PLL_SYS:
> @@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
>
> return 25000000 * (div + (div >> 1) + 1);
> + case PLL_AUDIO:
> + div = __raw_readl(&imx_ccm->analog_pll_audio);
> + if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
> + return 0;
> + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
> + if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
> + return MXC_HCLK;
> + pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
> + pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
> + test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
> + BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
> + div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
> + if (test_div == 3) {
> + debug("Error test_div\n");
> + return 0;
> + }
> + test_div = 1 << (2 - test_div);
> +
> + return infreq * (div + pll_num / pll_denom) / test_div;
> + case PLL_VIDEO:
> + div = __raw_readl(&imx_ccm->analog_pll_video);
> + if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
> + return 0;
> + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
> + if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
> + return MXC_HCLK;
> + pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
> + pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
> + test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
> + BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
> + div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
> + if (test_div == 3) {
> + debug("Error test_div\n");
> + return 0;
> + }
> + test_div = 1 << (2 - test_div);
> +
> + return infreq * (div + pll_num / pll_denom) / test_div;
> default:
> return 0;
> }
> @@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
> u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
> u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
>
> - u32 freq, podf, per2_clk2_podf;
> + u32 freq, podf, per2_clk2_podf, misc2_audio_div;
>
> if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
> is_cpu_type(MXC_CPU_MX6SL)) {
> @@ -472,9 +512,24 @@ static u32 get_mmdc_ch0_clk(void)
> freq = mxc_get_pll_pfd(PLL_BUS, 0);
> break;
> case 3:
> - /* static / 2 divider */
> - freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
Your indentation is off here (1 tab too shallow):
Finding the register would also have been easier if this were named
pmu_misc2.
> + misc2_audio_div = ((__raw_readl(&imx_ccm->ana_misc2)
> + >> 22) & 2) |
> + ((__raw_readl(&imx_ccm->ana_misc2)
> + >> 15) & 1);
> + switch (misc2_audio_div) {
> + case 0:
> + case 2:
> + misc2_audio_div = 1;
> + break;
> + case 1:
> + misc2_audio_div = 2;
> break;
> + case 3:
> + misc2_audio_div = 4;
> + break;
> + }
> + freq = decode_pll(PLL_AUDIO, MXC_HCLK) / misc2_audio_div;
> + break;
> }
> }
> return freq / (podf + 1) / (per2_clk2_podf + 1);
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg
2016-01-05 18:21 ` [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Eric Nelson
@ 2016-01-06 1:39 ` Peng Fan
0 siblings, 0 replies; 6+ messages in thread
From: Peng Fan @ 2016-01-06 1:39 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Tue, Jan 05, 2016 at 11:21:25AM -0700, Eric Nelson wrote:
>Hi Peng,
>
>On 01/03/2016 11:10 PM, Peng Fan wrote:
>> Add more entries for structure mxc_ccm_reg.
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> arch/arm/include/asm/arch-mx6/crm_regs.h | 87 ++++++++++++++++++++++++++++++++
>> 1 file changed, 87 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> index 13e0a3d..787eb68 100644
>> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> @@ -103,6 +103,93 @@ struct mxc_ccm_reg {
>> u32 analog_pfd_528_set;
>> u32 analog_pfd_528_clr;
>> u32 analog_pfd_528_tog;
>
>I'd like to see some comments here about where in the reference manuals
>these registers are defined, since they're not in the CCM section.
Will add comments in V2. Thanks for comments.
>
>Also, I think these should be named to match the RM
>i.e. pmu_reg_1p1
Yeah.
>
>> + u32 reg_1p1;
>> + u32 reg_1p1_set;
>> + u32 reg_1p1_clr;
>> + u32 reg_1p1_tog;
>> + u32 reg_3p0;
>> + u32 reg_3p0_set;
>> + u32 reg_3p0_clr;
>> + u32 reg_3p0_tog;
>> + u32 reg_2p5;
>> + u32 reg_2p5_set;
>> + u32 reg_2p5_clr;
>> + u32 reg_2p5_tog;
>> + u32 reg_core;
>> + u32 reg_core_set;
>> + u32 reg_core_clr;
>> + u32 reg_core_tog;
The upper are from pmu chapter.
>> + u32 ana_misc0;
>> + u32 ana_misc0_set;
>> + u32 ana_misc0_clr;
>> + u32 ana_misc0_tog;
>> + u32 ana_misc1;
>> + u32 ana_misc1_set;
>> + u32 ana_misc1_clr;
>> + u32 ana_misc1_tog;
>> + u32 ana_misc2;
>> + u32 ana_misc2_set;
>> + u32 ana_misc2_clr;
>
>... pmu_misc2_tog
>
>> + u32 ana_misc2_tog;
The upper registers are shared between CCM_ANALOG_MISCx and PMU_MISCx.
>
>TEMPMON registers
>
>> + u32 tempsense0;
>> + u32 tempsense0_set;
>> + u32 tempsense0_clr;
>> + u32 tempsense0_tog;
>> + u32 tempsense1;
>> + u32 tempsense1_set;
>> + u32 tempsense1_clr;
>> + u32 tempsense1_tog;
>
>... and USB_ANALOG here
>> + u32 usb1_vbus_detect;
>> + u32 usb1_vbus_detect_set;
>> + u32 usb1_vbus_detect_clr;
>> + u32 usb1_vbus_detect_tog;
>> + u32 usb1_chrg_detect;
>> + u32 usb1_chrg_detect_set;
>> + u32 usb1_chrg_detect_clr;
>> + u32 usb1_chrg_detect_tog;
>> + u32 usb1_vbus_det_stat;
>> + u32 usb1_vbus_det_stat_set;
>> + u32 usb1_vbus_det_stat_clr;
>> + u32 usb1_vbus_det_stat_tog;
>> + u32 usb1_chrg_det_stat;
>> + u32 usb1_chrg_det_stat_set;
>> + u32 usb1_chrg_det_stat_clr;
>> + u32 usb1_chrg_det_stat_tog;
>> + u32 usb1_loopback;
>> + u32 usb1_loopback_set;
>> + u32 usb1_loopback_clr;
>> + u32 usb1_loopback_tog;
>> + u32 usb1_misc;
>> + u32 usb1_misc_set;
>> + u32 usb1_misc_clr;
>> + u32 usb1_misc_tog;
>> + u32 usb2_vbus_detect;
>> + u32 usb2_vbus_detect_set;
>> + u32 usb2_vbus_detect_clr;
>> + u32 usb2_vbus_detect_tog;
>> + u32 usb2_chrg_detect;
>> + u32 usb2_chrg_detect_set;
>> + u32 usb2_chrg_detect_clr;
>> + u32 usb2_chrg_detect_tog;
>> + u32 usb2_vbus_det_stat;
>> + u32 usb2_vbus_det_stat_set;
>> + u32 usb2_vbus_det_stat_clr;
>> + u32 usb2_vbus_det_stat_tog;
>> + u32 usb2_chrg_det_stat;
>> + u32 usb2_chrg_det_stat_set;
>> + u32 usb2_chrg_det_stat_clr;
>> + u32 usb2_chrg_det_stat_tog;
>> + u32 usb2_loopback;
>> + u32 usb2_loopback_set;
>> + u32 usb2_loopback_clr;
>> + u32 usb2_loopback_tog;
>> + u32 usb2_misc;
>> + u32 usb2_misc_set;
>> + u32 usb2_misc_clr;
>> + u32 usb2_misc_tog;
>> + u32 digprog;
>> + u32 reserved1[7];
>> + u32 digprog_sololite;
>> };
>> #endif
>>
>>
>
>Otherwise, I checked these against the i.MX6DQ/SDL/SL and UL manuals
>(not i.MX6SX), and
i.MX6SX has same map.
>
>Reviewed-By: Eric Nelson <eric@nelint.com>
Thanks,
Peng.
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation
2016-01-05 19:06 ` Eric Nelson
@ 2016-01-06 1:47 ` Peng Fan
0 siblings, 0 replies; 6+ messages in thread
From: Peng Fan @ 2016-01-06 1:47 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Tue, Jan 05, 2016 at 12:06:52PM -0700, Eric Nelson wrote:
>Hi Peng,
>
>On 01/03/2016 11:10 PM, Peng Fan wrote:
>> Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
>> Processor Reference Manual and "Figure 18-5. BUS clock generation" of
>> i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
>> sources from pll4_main_clk(pll_audio), the calculation is wrong.
>>
>> Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
>> for decode_pll.
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> arch/arm/cpu/armv7/mx6/clock.c | 63 +++++++++++++++++++++++++++++++++++++++---
>> 1 file changed, 59 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
>> index 64514b1..1506c04 100644
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -18,6 +18,8 @@ enum pll_clocks {
>> PLL_BUS, /* System Bus PLL*/
>> PLL_USBOTG, /* OTG USB PLL */
>> PLL_ENET, /* ENET PLL */
>> + PLL_AUDIO, /* AUDIO PLL */
>> + PLL_VIDEO, /* AUDIO PLL */
>> };
>>
>> struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>> @@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
>> }
>> static u32 decode_pll(enum pll_clocks pll, u32 infreq)
>> {
>> - u32 div;
>> + u32 div, test_div, pll_num, pll_denom;
>>
>> switch (pll) {
>> case PLL_SYS:
>> @@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
>> div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
>>
>> return 25000000 * (div + (div >> 1) + 1);
>> + case PLL_AUDIO:
>> + div = __raw_readl(&imx_ccm->analog_pll_audio);
>> + if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
>> + return 0;
>> + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
>> + if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
>> + return MXC_HCLK;
>> + pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
>> + pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
>> + test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
>> + BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
>> + div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
>> + if (test_div == 3) {
>> + debug("Error test_div\n");
>> + return 0;
>> + }
>> + test_div = 1 << (2 - test_div);
>> +
>> + return infreq * (div + pll_num / pll_denom) / test_div;
>> + case PLL_VIDEO:
>> + div = __raw_readl(&imx_ccm->analog_pll_video);
>> + if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
>> + return 0;
>> + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
>> + if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
>> + return MXC_HCLK;
>> + pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
>> + pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
>> + test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
>> + BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
>> + div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
>> + if (test_div == 3) {
>> + debug("Error test_div\n");
>> + return 0;
>> + }
>> + test_div = 1 << (2 - test_div);
>> +
>> + return infreq * (div + pll_num / pll_denom) / test_div;
>> default:
>> return 0;
>> }
>> @@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
>> u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
>> u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
>>
>> - u32 freq, podf, per2_clk2_podf;
>> + u32 freq, podf, per2_clk2_podf, misc2_audio_div;
>>
>> if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
>> is_cpu_type(MXC_CPU_MX6SL)) {
>> @@ -472,9 +512,24 @@ static u32 get_mmdc_ch0_clk(void)
>> freq = mxc_get_pll_pfd(PLL_BUS, 0);
>> break;
>> case 3:
>> - /* static / 2 divider */
>> - freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
>
>Your indentation is off here (1 tab too shallow):
oh. Thanks for pointing this out.
>
>Finding the register would also have been easier if this were named
>pmu_misc2.
CCM_ANALOG_MISCx is same to PMU_MISCx, they have same address.
Thanks
Peng.
>
>> + misc2_audio_div = ((__raw_readl(&imx_ccm->ana_misc2)
>> + >> 22) & 2) |
>> + ((__raw_readl(&imx_ccm->ana_misc2)
>> + >> 15) & 1);
>> + switch (misc2_audio_div) {
>> + case 0:
>> + case 2:
>> + misc2_audio_div = 1;
>> + break;
>> + case 1:
>> + misc2_audio_div = 2;
>> break;
>> + case 3:
>> + misc2_audio_div = 4;
>> + break;
>> + }
>> + freq = decode_pll(PLL_AUDIO, MXC_HCLK) / misc2_audio_div;
>> + break;
>> }
>> }
>> return freq / (podf + 1) / (per2_clk2_podf + 1);
>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-06 1:47 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-01-04 6:10 [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Peng Fan
2016-01-04 6:10 ` [U-Boot] [PATCH 2/2] imx: mx6ul/sx: fix mmdc_ch0 clk calculation Peng Fan
2016-01-05 19:06 ` Eric Nelson
2016-01-06 1:47 ` Peng Fan
2016-01-05 18:21 ` [U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg Eric Nelson
2016-01-06 1:39 ` Peng Fan
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