From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 12 Jan 2016 23:16:44 +0100
Subject: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines
	for Arria10
In-Reply-To: <56957A1E.90302@kernel.org>
References: <1452632204-22047-1-git-send-email-dinguyen@opensource.altera.com>
 <201601122302.28242.marex@denx.de> <56957A1E.90302@kernel.org>
Message-ID: <201601122316.44121.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
> On 01/12/2016 04:02 PM, Marek Vasut wrote:
> > On Tuesday, January 12, 2016 at 09:56:42 PM,
> > dinguyen at opensource.altera.com
> > 
> > wrote:
> >> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> >> 
> >> Add the Arria10 reset manager defines that is used in Linux. Change the
> >> license to SPDX.
> >> 
> >> [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
> >> 
> >> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> > 
> > Applied all three to u-boot-socfpga/02-arria10 , thanks!
> > 
> > btw what's the status of A10 ? What will I be able to compile it (and
> > thus merge the stuff into mainline and ev. use it on actual A10) ? A
> > board would be nice too ;-)
> 
> Here is my list of to-do that is left for A10:
> 
> - submit SDRAM controller
> - rework FPGA manager for A10
> - port an SPL for A10
> 
> I think the most work will be the SDRAM controller as it needs quite a
> bit of cleanup. I'm about ~25% through with that.

Didn't you mention that you use nios2 that magically does that init for you?
Shall I expect thousands of LoC SDRAM controller driver again or is there 
something "lighter" coming up ? ;-)

> As for HW, I'll see what I can do.

Don't worry about it too much. I also poked Chin about it some time ago, but
I dunno where he got with this.

Thanks!

Best regards,
Marek Vasut