From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 13 Jan 2016 03:04:49 +0100
Subject: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines
	for Arria10
In-Reply-To: <1452650322.2108.5.camel@altera.com>
References: <1452632204-22047-1-git-send-email-dinguyen@opensource.altera.com>
 <201601122316.44121.marex@denx.de> <1452650322.2108.5.camel@altera.com>
Message-ID: <201601130304.49243.marex@denx.de>
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To: u-boot@lists.denx.de

On Wednesday, January 13, 2016 at 02:58:42 AM, Chin Liang See wrote:
> On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote:
> > On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
> > > On 01/12/2016 04:02 PM, Marek Vasut wrote:
> > > > On Tuesday, January 12, 2016 at 09:56:42 PM,
> > > > dinguyen at opensource.altera.com
> > > > 
> > > > wrote:
> > > > > From: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > 
> > > > > Add the Arria10 reset manager defines that is used in Linux.
> > > > > Change the
> > > > > license to SPDX.
> > > > > 
> > > > > [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux
> > > > > kernel]
> > > > > 
> > > > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > 
> > > > Applied all three to u-boot-socfpga/02-arria10 , thanks!
> > > > 
> > > > btw what's the status of A10 ? What will I be able to compile it
> > > > (and
> > > > thus merge the stuff into mainline and ev. use it on actual A10)
> > > > ? A
> > > > board would be nice too ;-)
> > > 
> > > Here is my list of to-do that is left for A10:
> > > 
> > > - submit SDRAM controller
> > > - rework FPGA manager for A10
> > > - port an SPL for A10
> > > 
> > > I think the most work will be the SDRAM controller as it needs
> > > quite a
> > > bit of cleanup. I'm about ~25% through with that.
> > 
> > Didn't you mention that you use nios2 that magically does that init
> > for you?
> > Shall I expect thousands of LoC SDRAM controller driver again or is
> > there
> > something "lighter" coming up ? ;-)
> 
> Yah it should be lighter as all SDRAM configuration now part of
> bitstream. Driver just need to derive the value from bitstream register
> and setup the DDR controller. No more DDR handoff.

Whew :)

> > > As for HW, I'll see what I can do.
> > 
> > Don't worry about it too much. I also poked Chin about it some time
> > ago, but
> > I dunno where he got with this.
> 
> I am still working on this. We have limited boards as we will be
> getting production board in a month time. Dinh, you have any boards to
> spare? Most of boards here already went into test farms.

I'll wait for the production ones , no need to hurry :)

Best regards,
Marek Vasut