[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support

[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support

[Stefan Roese]

Hi!

So this is my 4th posting regarding the Candence SPI driver on SoCFPGA.

Again, SPI NOR flash is working. At least on SoCrates and on another
custom SoCFPGA based board. The main change in this version is, that
the Cadence driver now is a driver model (DM) based driver. And this
needs the DT support which I posted just before.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that I have patches to support the Designware SPI master
controller also via DM in the queue. I'll post them shortly.

Thanks,
Stefan

Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
v4:
- Reworked to support driver model (DM)
- Coding-style changes to make it checkpatch clean

v3:
- Added SPDX License Indentifier
- Removed CQSPI_WRITEL / CQSPI_READL

 drivers/spi/Makefile           |   1 +
 drivers/spi/cadence_qspi.c     | 345 ++++++++++++++++
 drivers/spi/cadence_qspi.h     |  76 ++++
 drivers/spi/cadence_qspi_apb.c | 898 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 1320 insertions(+)
 create mode 100644 drivers/spi/cadence_qspi.c
 create mode 100644 drivers/spi/cadence_qspi.h
 create mode 100644 drivers/spi/cadence_qspi_apb.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index eabbf27..964fdc1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 0000000..fa95b19
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include "cadence_qspi.h"
+
+#define CQSPI_STIG_READ			0
+#define CQSPI_STIG_WRITE		1
+#define CQSPI_INDIRECT_READ		2
+#define CQSPI_INDIRECT_WRITE		3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cadence_spi_write_speed(struct udevice *bus, uint hz)
+{
+	struct cadence_spi_platdata *plat = bus->platdata;
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+	cadence_qspi_apb_config_baudrate_div(priv->regbase,
+					     CONFIG_CQSPI_REF_CLK, hz);
+
+	/* Reconfigure delay timing if speed is changed. */
+	cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+			       plat->tshsl_ns, plat->tsd2d_ns,
+			       plat->tchsh_ns, plat->tslch_ns);
+
+	return 0;
+}
+
+/* Calibration sequence to determine the read data capture delay register */
+static int spi_calibration(struct udevice *bus)
+{
+	struct cadence_spi_platdata *plat = bus->platdata;
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	void *base = priv->regbase;
+	u8 opcode_rdid = 0x9F;
+	unsigned int idcode = 0, temp = 0;
+	int err = 0, i, range_lo = -1, range_hi = -1;
+
+	/* start with slowest clock (1 MHz) */
+	cadence_spi_write_speed(bus, 1000000);
+
+	/* configure the read data capture delay register to 0 */
+	cadence_qspi_apb_readdata_capture(base, 1, 0);
+
+	/* Enable QSPI */
+	cadence_qspi_apb_controller_enable(base);
+
+	/* read the ID which will be our golden value */
+	err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+		3, (u8 *)&idcode);
+	if (err) {
+		puts("SF: Calibration failed (read)\n");
+		return err;
+	}
+
+	/* use back the intended clock and find low range */
+	cadence_spi_write_speed(bus, plat->max_hz);
+	for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
+		/* Disable QSPI */
+		cadence_qspi_apb_controller_disable(base);
+
+		/* reconfigure the read data capture delay register */
+		cadence_qspi_apb_readdata_capture(base, 1, i);
+
+		/* Enable back QSPI */
+		cadence_qspi_apb_controller_enable(base);
+
+		/* issue a RDID to get the ID value */
+		err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+			3, (u8 *)&temp);
+		if (err) {
+			puts("SF: Calibration failed (read)\n");
+			return err;
+		}
+
+		/* search for range lo */
+		if (range_lo == -1 && temp == idcode) {
+			range_lo = i;
+			continue;
+		}
+
+		/* search for range hi */
+		if (range_lo != -1 && temp != idcode) {
+			range_hi = i - 1;
+			break;
+		}
+		range_hi = i;
+	}
+
+	if (range_lo == -1) {
+		puts("SF: Calibration failed (low range)\n");
+		return err;
+	}
+
+	/* Disable QSPI for subsequent initialization */
+	cadence_qspi_apb_controller_disable(base);
+
+	/* configure the final value for read data capture delay register */
+	cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
+	debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
+	      (range_hi + range_lo) / 2, range_lo, range_hi);
+
+	/* just to ensure we do once only when speed or chip select change */
+	priv->qspi_calibrated_hz = plat->max_hz;
+	priv->qspi_calibrated_cs = spi_chip_select(bus);
+
+	return 0;
+}
+
+static int cadence_spi_set_speed(struct udevice *bus, uint hz)
+{
+	struct cadence_spi_platdata *plat = bus->platdata;
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	int err;
+
+	/* Disable QSPI */
+	cadence_qspi_apb_controller_disable(priv->regbase);
+
+	cadence_spi_write_speed(bus, hz);
+
+	/* Calibration required for different SCLK speed or chip select */
+	if (priv->qspi_calibrated_hz != plat->max_hz ||
+	    priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+		err = spi_calibration(bus);
+		if (err)
+			return err;
+	}
+
+	/* Enable QSPI */
+	cadence_qspi_apb_controller_enable(priv->regbase);
+
+	debug("%s: speed=%d\n", __func__, hz);
+
+	return 0;
+}
+
+static int cadence_spi_probe(struct udevice *bus)
+{
+	struct cadence_spi_platdata *plat = bus->platdata;
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+	priv->regbase = plat->regbase;
+	priv->ahbbase = plat->ahbbase;
+
+	if (!priv->qspi_is_init) {
+		cadence_qspi_apb_controller_init(plat);
+		priv->qspi_is_init = 1;
+	}
+
+	return 0;
+}
+
+static int cadence_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
+	unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
+
+	/* Disable QSPI */
+	cadence_qspi_apb_controller_disable(priv->regbase);
+
+	/* Set SPI mode */
+	cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+
+	/* Enable QSPI */
+	cadence_qspi_apb_controller_enable(priv->regbase);
+
+	return 0;
+}
+
+static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			    const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct cadence_spi_platdata *plat = bus->platdata;
+	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	void *base = priv->regbase;
+	u8 *cmd_buf = priv->cmd_buf;
+	size_t data_bytes;
+	int err = 0;
+	u32 mode = CQSPI_STIG_WRITE;
+
+	if (flags & SPI_XFER_BEGIN) {
+		/* copy command to local buffer */
+		priv->cmd_len = bitlen / 8;
+		memcpy(cmd_buf, dout, priv->cmd_len);
+	}
+
+	if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
+		/* if start and end bit are set, the data bytes is 0. */
+		data_bytes = 0;
+	} else {
+		data_bytes = bitlen / 8;
+	}
+	debug("%s: len=%d [bytes]\n", __func__, data_bytes);
+
+	/* Set Chip select */
+	cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
+				    CONFIG_CQSPI_DECODER);
+
+	if ((flags & SPI_XFER_END) || (flags == 0)) {
+		if (priv->cmd_len == 0) {
+			printf("QSPI: Error, command is empty.\n");
+			return -1;
+		}
+
+		if (din && data_bytes) {
+			/* read */
+			/* Use STIG if no address. */
+			if (!CQSPI_IS_ADDR(priv->cmd_len))
+				mode = CQSPI_STIG_READ;
+			else
+				mode = CQSPI_INDIRECT_READ;
+		} else if (dout && !(flags & SPI_XFER_BEGIN)) {
+			/* write */
+			if (!CQSPI_IS_ADDR(priv->cmd_len))
+				mode = CQSPI_STIG_WRITE;
+			else
+				mode = CQSPI_INDIRECT_WRITE;
+		}
+
+		switch (mode) {
+		case CQSPI_STIG_READ:
+			err = cadence_qspi_apb_command_read(
+				base, priv->cmd_len, cmd_buf,
+				data_bytes, din);
+
+		break;
+		case CQSPI_STIG_WRITE:
+			err = cadence_qspi_apb_command_write(base,
+				priv->cmd_len, cmd_buf,
+				data_bytes, dout);
+		break;
+		case CQSPI_INDIRECT_READ:
+			err = cadence_qspi_apb_indirect_read_setup(plat,
+				priv->cmd_len, cmd_buf);
+			if (!err) {
+				err = cadence_qspi_apb_indirect_read_execute
+				(plat, data_bytes, din);
+			}
+		break;
+		case CQSPI_INDIRECT_WRITE:
+			err = cadence_qspi_apb_indirect_write_setup
+				(plat, priv->cmd_len, cmd_buf);
+			if (!err) {
+				err = cadence_qspi_apb_indirect_write_execute
+				(plat, data_bytes, dout);
+			}
+		break;
+		default:
+			err = -1;
+			break;
+		}
+
+		if (flags & SPI_XFER_END) {
+			/* clear command buffer */
+			memset(cmd_buf, 0, sizeof(priv->cmd_buf));
+			priv->cmd_len = 0;
+		}
+	}
+
+	return err;
+}
+
+static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct cadence_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+	int subnode;
+	u32 data[4];
+	int ret;
+
+	/* 2 base addresses are needed, lets get them from the DT */
+	ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
+	if (ret) {
+		printf("Error: Can't get base addresses (ret=%d)!\n", ret);
+		return -ENODEV;
+	}
+
+	plat->regbase = (void *)data[0];
+	plat->ahbbase = (void *)data[2];
+
+	/* Use 500KHz as a suitable default */
+	plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+				      500000);
+
+	/* All other paramters are embedded in the child node */
+	subnode = fdt_first_subnode(blob, node);
+	if (!subnode) {
+		printf("Error: subnode with SPI flash config missing!\n");
+		return -ENODEV;
+	}
+
+	/* Read other parameters from DT */
+	plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
+	plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
+	plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
+	plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
+	plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
+	plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+
+	debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
+	      __func__, plat->regbase, plat->ahbbase, plat->max_hz,
+	      plat->page_size);
+
+	return 0;
+}
+
+static const struct dm_spi_ops cadence_spi_ops = {
+	.xfer		= cadence_spi_xfer,
+	.set_speed	= cadence_spi_set_speed,
+	.set_mode	= cadence_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id cadence_spi_ids[] = {
+	{ .compatible = "cadence,qspi" },
+	{ }
+};
+
+U_BOOT_DRIVER(cadence_spi) = {
+	.name = "cadence_spi",
+	.id = UCLASS_SPI,
+	.of_match = cadence_spi_ids,
+	.ops = &cadence_spi_ops,
+	.ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
+	.per_child_auto_alloc_size = sizeof(struct spi_slave),
+	.probe = cadence_spi_probe,
+};
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
new file mode 100644
index 0000000..c9a6142
--- /dev/null
+++ b/drivers/spi/cadence_qspi.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CADENCE_QSPI_H__
+#define __CADENCE_QSPI_H__
+
+#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
+
+#define CQSPI_NO_DECODER_MAX_CS		4
+#define CQSPI_DECODER_MAX_CS		16
+#define CQSPI_READ_CAPTURE_MAX_DELAY	16
+
+struct cadence_spi_platdata {
+	unsigned int	max_hz;
+	void		*regbase;
+	void		*ahbbase;
+
+	u32		page_size;
+	u32		block_size;
+	u32		tshsl_ns;
+	u32		tsd2d_ns;
+	u32		tchsh_ns;
+	u32		tslch_ns;
+};
+
+struct cadence_spi_priv {
+	void		*regbase;
+	void		*ahbbase;
+	size_t		cmd_len;
+	u8		cmd_buf[32];
+	size_t		data_len;
+
+	int		qspi_is_init;
+	unsigned int	qspi_calibrated_hz;
+	unsigned int	qspi_calibrated_cs;
+};
+
+/* Functions call declaration */
+void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
+void cadence_qspi_apb_controller_enable(void *reg_base_addr);
+void cadence_qspi_apb_controller_disable(void *reg_base_addr);
+
+int cadence_qspi_apb_command_read(void *reg_base_addr,
+	unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
+int cadence_qspi_apb_command_write(void *reg_base_addr,
+	unsigned int cmdlen, const u8 *cmdbuf,
+	unsigned int txlen,  const u8 *txbuf);
+
+int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
+	unsigned int cmdlen, const u8 *cmdbuf);
+int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+	unsigned int rxlen, u8 *rxbuf);
+int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
+	unsigned int cmdlen, const u8 *cmdbuf);
+int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+	unsigned int txlen, const u8 *txbuf);
+
+void cadence_qspi_apb_chipselect(void *reg_base,
+	unsigned int chip_select, unsigned int decoder_enable);
+void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
+	unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_config_baudrate_div(void *reg_base,
+	unsigned int ref_clk_hz, unsigned int sclk_hz);
+void cadence_qspi_apb_delay(void *reg_base,
+	unsigned int ref_clk, unsigned int sclk_hz,
+	unsigned int tshsl_ns, unsigned int tsd2d_ns,
+	unsigned int tchsh_ns, unsigned int tslch_ns);
+void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
+void cadence_qspi_apb_readdata_capture(void *reg_base,
+	unsigned int bypass, unsigned int delay);
+
+#endif /* __CADENCE_QSPI_H__ */
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
new file mode 100644
index 0000000..00a115f
--- /dev/null
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -0,0 +1,898 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of the Altera Corporation nor the
+ *    names of its contributors may be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "cadence_qspi.h"
+
+#define CQSPI_REG_POLL_US			(1) /* 1us */
+#define CQSPI_REG_RETRY				(10000)
+#define CQSPI_POLL_IDLE_RETRY			(3)
+
+#define CQSPI_FIFO_WIDTH			(4)
+
+/* Controller sram size in word */
+#define CQSPI_REG_SRAM_SIZE_WORD		(128)
+#define CQSPI_REG_SRAM_RESV_WORDS		(2)
+#define CQSPI_REG_SRAM_PARTITION_WR		(1)
+#define CQSPI_REG_SRAM_PARTITION_RD		\
+	(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
+#define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
+
+/* Transfer mode */
+#define CQSPI_INST_TYPE_SINGLE			(0)
+#define CQSPI_INST_TYPE_DUAL			(1)
+#define CQSPI_INST_TYPE_QUAD			(2)
+
+#define CQSPI_STIG_DATA_LEN_MAX			(8)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		(0xFFFFF)
+
+#define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
+#define CQSPI_DUMMY_BYTES_MAX			(4)
+
+
+#define CQSPI_REG_SRAM_FILL_THRESHOLD	\
+	((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
+/****************************************************************************
+ * Controller's configuration and status register (offset from QSPI_BASE)
+ ****************************************************************************/
+#define	CQSPI_REG_CONFIG			0x00
+#define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
+#define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
+#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
+#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
+#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
+#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
+#define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
+#define	CQSPI_REG_CONFIG_BAUD_LSB		19
+#define	CQSPI_REG_CONFIG_IDLE_LSB		31
+#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
+#define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
+
+#define	CQSPI_REG_RD_INSTR			0x04
+#define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
+#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB	8
+#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB	12
+#define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
+#define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
+#define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
+#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
+#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
+#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
+#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
+
+#define	CQSPI_REG_WR_INSTR			0x08
+#define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
+
+#define	CQSPI_REG_DELAY				0x0C
+#define	CQSPI_REG_DELAY_TSLCH_LSB		0
+#define	CQSPI_REG_DELAY_TCHSH_LSB		8
+#define	CQSPI_REG_DELAY_TSD2D_LSB		16
+#define	CQSPI_REG_DELAY_TSHSL_LSB		24
+#define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
+#define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
+#define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
+#define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
+
+#define	CQSPI_READLCAPTURE			0x10
+#define	CQSPI_READLCAPTURE_BYPASS_LSB		0
+#define	CQSPI_READLCAPTURE_DELAY_LSB		1
+#define	CQSPI_READLCAPTURE_DELAY_MASK		0xF
+
+#define	CQSPI_REG_SIZE				0x14
+#define	CQSPI_REG_SIZE_ADDRESS_LSB		0
+#define	CQSPI_REG_SIZE_PAGE_LSB			4
+#define	CQSPI_REG_SIZE_BLOCK_LSB		16
+#define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
+#define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
+#define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
+
+#define	CQSPI_REG_SRAMPARTITION			0x18
+#define	CQSPI_REG_INDIRECTTRIGGER		0x1C
+
+#define	CQSPI_REG_REMAP				0x24
+#define	CQSPI_REG_MODE_BIT			0x28
+
+#define	CQSPI_REG_SDRAMLEVEL			0x2C
+#define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
+#define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
+#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
+#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
+
+#define	CQSPI_REG_IRQSTATUS			0x40
+#define	CQSPI_REG_IRQMASK			0x44
+
+#define	CQSPI_REG_INDIRECTRD			0x60
+#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 << 0)
+#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
+#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
+#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 << 5)
+
+#define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
+#define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
+#define	CQSPI_REG_INDIRECTRDBYTES		0x6C
+
+#define	CQSPI_REG_CMDCTRL			0x90
+#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 << 0)
+#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
+#define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
+#define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
+#define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
+#define	CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
+#define	CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
+#define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
+#define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
+#define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
+#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
+#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
+#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
+#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
+#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
+
+#define	CQSPI_REG_INDIRECTWR			0x70
+#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 << 0)
+#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
+#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 << 2)
+#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 << 5)
+
+#define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
+#define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
+#define	CQSPI_REG_INDIRECTWRBYTES		0x7C
+
+#define	CQSPI_REG_CMDADDRESS			0x94
+#define	CQSPI_REG_CMDREADDATALOWER		0xA0
+#define	CQSPI_REG_CMDREADDATAUPPER		0xA4
+#define	CQSPI_REG_CMDWRITEDATALOWER		0xA8
+#define	CQSPI_REG_CMDWRITEDATAUPPER		0xAC
+
+#define CQSPI_REG_IS_IDLE(base)					\
+	((readl(base + CQSPI_REG_CONFIG) >>		\
+		CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
+
+#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)		\
+	((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
+
+#define CQSPI_GET_RD_SRAM_LEVEL(reg_base)			\
+	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
+	CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
+
+#define CQSPI_GET_WR_SRAM_LEVEL(reg_base)			\
+	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
+	CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
+
+static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
+	unsigned int addr_width)
+{
+	unsigned int addr;
+
+	addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
+
+	if (addr_width == 4)
+		addr = (addr << 8) | addr_buf[3];
+
+	return addr;
+}
+
+static void cadence_qspi_apb_read_fifo_data(void *dest,
+	const void *src_ahb_addr, unsigned int bytes)
+{
+	unsigned int temp;
+	int remaining = bytes;
+	unsigned int *dest_ptr = (unsigned int *)dest;
+	unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
+
+	while (remaining > 0) {
+		if (remaining >= CQSPI_FIFO_WIDTH) {
+			*dest_ptr = readl(src_ptr);
+			remaining -= CQSPI_FIFO_WIDTH;
+		} else {
+			/* dangling bytes */
+			temp = readl(src_ptr);
+			memcpy(dest_ptr, &temp, remaining);
+			break;
+		}
+		dest_ptr++;
+	}
+
+	return;
+}
+
+static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
+	const void *src, unsigned int bytes)
+{
+	unsigned int temp;
+	int remaining = bytes;
+	unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
+	unsigned int *src_ptr = (unsigned int *)src;
+
+	while (remaining > 0) {
+		if (remaining >= CQSPI_FIFO_WIDTH) {
+			writel(*src_ptr, dest_ptr);
+			remaining -= sizeof(unsigned int);
+		} else {
+			/* dangling bytes */
+			memcpy(&temp, src_ptr, remaining);
+			writel(temp, dest_ptr);
+			break;
+		}
+		src_ptr++;
+	}
+
+	return;
+}
+
+/* Read from SRAM FIFO with polling SRAM fill level. */
+static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
+			const void *src_addr,  unsigned int num_bytes)
+{
+	unsigned int remaining = num_bytes;
+	unsigned int retry;
+	unsigned int sram_level = 0;
+	unsigned char *dest = (unsigned char *)dest_addr;
+
+	while (remaining > 0) {
+		retry = CQSPI_REG_RETRY;
+		while (retry--) {
+			sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
+			if (sram_level)
+				break;
+			udelay(1);
+		}
+
+		if (!retry) {
+			printf("QSPI: No receive data after polling for %d times\n",
+			       CQSPI_REG_RETRY);
+			return -1;
+		}
+
+		sram_level *= CQSPI_FIFO_WIDTH;
+		sram_level = sram_level > remaining ? remaining : sram_level;
+
+		/* Read data from FIFO. */
+		cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
+		dest += sram_level;
+		remaining -= sram_level;
+		udelay(1);
+	}
+	return 0;
+}
+
+/* Write to SRAM FIFO with polling SRAM fill level. */
+static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
+				const void *src_addr, unsigned int num_bytes)
+{
+	const void *reg_base = plat->regbase;
+	void *dest_addr = plat->ahbbase;
+	unsigned int retry = CQSPI_REG_RETRY;
+	unsigned int sram_level;
+	unsigned int wr_bytes;
+	unsigned char *src = (unsigned char *)src_addr;
+	int remaining = num_bytes;
+	unsigned int page_size = plat->page_size;
+	unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
+
+	while (remaining > 0) {
+		retry = CQSPI_REG_RETRY;
+		while (retry--) {
+			sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
+			if (sram_level <= sram_threshold_words)
+				break;
+		}
+		if (!retry) {
+			printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
+			       sram_level, sram_threshold_words);
+			return -1;
+		}
+		/* Write a page or remaining bytes. */
+		wr_bytes = (remaining > page_size) ?
+					page_size : remaining;
+
+		cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
+		src += wr_bytes;
+		remaining -= wr_bytes;
+	}
+
+	return 0;
+}
+
+void cadence_qspi_apb_controller_enable(void *reg_base)
+{
+	unsigned int reg;
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+	return;
+}
+
+void cadence_qspi_apb_controller_disable(void *reg_base)
+{
+	unsigned int reg;
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+	return;
+}
+
+/* Return 1 if idle, otherwise return 0 (busy). */
+static unsigned int cadence_qspi_wait_idle(void *reg_base)
+{
+	unsigned int start, count = 0;
+	/* timeout in unit of ms */
+	unsigned int timeout = 5000;
+
+	start = get_timer(0);
+	for ( ; get_timer(start) < timeout ; ) {
+		if (CQSPI_REG_IS_IDLE(reg_base))
+			count++;
+		else
+			count = 0;
+		/*
+		 * Ensure the QSPI controller is in true idle state after
+		 * reading back the same idle status consecutively
+		 */
+		if (count >= CQSPI_POLL_IDLE_RETRY)
+			return 1;
+	}
+
+	/* Timeout, still in busy mode. */
+	printf("QSPI: QSPI is still busy after poll for %d times.\n",
+	       CQSPI_REG_RETRY);
+	return 0;
+}
+
+void cadence_qspi_apb_readdata_capture(void *reg_base,
+				unsigned int bypass, unsigned int delay)
+{
+	unsigned int reg;
+	cadence_qspi_apb_controller_disable(reg_base);
+
+	reg = readl(reg_base + CQSPI_READLCAPTURE);
+
+	if (bypass)
+		reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+	else
+		reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+
+	reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
+		<< CQSPI_READLCAPTURE_DELAY_LSB);
+
+	reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
+		<< CQSPI_READLCAPTURE_DELAY_LSB);
+
+	writel(reg, reg_base + CQSPI_READLCAPTURE);
+
+	cadence_qspi_apb_controller_enable(reg_base);
+	return;
+}
+
+void cadence_qspi_apb_config_baudrate_div(void *reg_base,
+	unsigned int ref_clk_hz, unsigned int sclk_hz)
+{
+	unsigned int reg;
+	unsigned int div;
+
+	cadence_qspi_apb_controller_disable(reg_base);
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
+
+	div = ref_clk_hz / sclk_hz;
+
+	if (div > 32)
+		div = 32;
+
+	/* Check if even number. */
+	if ((div & 1)) {
+		div = (div / 2);
+	} else {
+		if (ref_clk_hz % sclk_hz)
+			/* ensure generated SCLK doesn't exceed user
+			specified sclk_hz */
+			div = (div / 2);
+		else
+			div = (div / 2) - 1;
+	}
+
+	debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
+	      ref_clk_hz, sclk_hz, div);
+
+	div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
+	reg |= div;
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+	cadence_qspi_apb_controller_enable(reg_base);
+	return;
+}
+
+void cadence_qspi_apb_set_clk_mode(void *reg_base,
+	unsigned int clk_pol, unsigned int clk_pha)
+{
+	unsigned int reg;
+
+	cadence_qspi_apb_controller_disable(reg_base);
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	reg &= ~(1 <<
+		(CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
+
+	reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
+	reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
+
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+	cadence_qspi_apb_controller_enable(reg_base);
+	return;
+}
+
+void cadence_qspi_apb_chipselect(void *reg_base,
+	unsigned int chip_select, unsigned int decoder_enable)
+{
+	unsigned int reg;
+
+	cadence_qspi_apb_controller_disable(reg_base);
+
+	debug("%s : chipselect %d decode %d\n", __func__, chip_select,
+	      decoder_enable);
+
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	/* docoder */
+	if (decoder_enable) {
+		reg |= CQSPI_REG_CONFIG_DECODE_MASK;
+	} else {
+		reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
+		/* Convert CS if without decoder.
+		 * CS0 to 4b'1110
+		 * CS1 to 4b'1101
+		 * CS2 to 4b'1011
+		 * CS3 to 4b'0111
+		 */
+		chip_select = 0xF & ~(1 << chip_select);
+	}
+
+	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
+			<< CQSPI_REG_CONFIG_CHIPSELECT_LSB);
+	reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
+			<< CQSPI_REG_CONFIG_CHIPSELECT_LSB;
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+	cadence_qspi_apb_controller_enable(reg_base);
+	return;
+}
+
+void cadence_qspi_apb_delay(void *reg_base,
+	unsigned int ref_clk, unsigned int sclk_hz,
+	unsigned int tshsl_ns, unsigned int tsd2d_ns,
+	unsigned int tchsh_ns, unsigned int tslch_ns)
+{
+	unsigned int ref_clk_ns;
+	unsigned int sclk_ns;
+	unsigned int tshsl, tchsh, tslch, tsd2d;
+	unsigned int reg;
+
+	cadence_qspi_apb_controller_disable(reg_base);
+
+	/* Convert to ns. */
+	ref_clk_ns = (1000000000) / ref_clk;
+
+	/* Convert to ns. */
+	sclk_ns = (1000000000) / sclk_hz;
+
+	/* Plus 1 to round up 1 clock cycle. */
+	tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
+	tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
+	tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
+	tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+
+	reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
+			<< CQSPI_REG_DELAY_TSHSL_LSB);
+	reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
+			<< CQSPI_REG_DELAY_TCHSH_LSB);
+	reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
+			<< CQSPI_REG_DELAY_TSLCH_LSB);
+	reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
+			<< CQSPI_REG_DELAY_TSD2D_LSB);
+	writel(reg, reg_base + CQSPI_REG_DELAY);
+
+	cadence_qspi_apb_controller_enable(reg_base);
+	return;
+}
+
+void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
+{
+	unsigned reg;
+
+	cadence_qspi_apb_controller_disable(plat->regbase);
+
+	/* Configure the device size and address bytes */
+	reg = readl(plat->regbase + CQSPI_REG_SIZE);
+	/* Clear the previous value */
+	reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
+	reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
+	reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
+	reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
+	writel(reg, plat->regbase + CQSPI_REG_SIZE);
+
+	/* Configure the remap address register, no remap */
+	writel(0, plat->regbase + CQSPI_REG_REMAP);
+
+	/* Disable all interrupts */
+	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
+
+	cadence_qspi_apb_controller_enable(plat->regbase);
+	return;
+}
+
+static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
+	unsigned int reg)
+{
+	unsigned int retry = CQSPI_REG_RETRY;
+
+	/* Write the CMDCTRL without start execution. */
+	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
+	/* Start execute */
+	reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
+	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
+
+	while (retry--) {
+		reg = readl(reg_base + CQSPI_REG_CMDCTRL);
+		if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
+			break;
+		udelay(1);
+	}
+
+	if (!retry) {
+		printf("QSPI: flash command execution timeout\n");
+		return -EIO;
+	}
+
+	/* Polling QSPI idle status. */
+	if (!cadence_qspi_wait_idle(reg_base))
+		return -EIO;
+
+	return 0;
+}
+
+/* For command RDID, RDSR. */
+int cadence_qspi_apb_command_read(void *reg_base,
+	unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
+	u8 *rxbuf)
+{
+	unsigned int reg;
+	unsigned int read_len;
+	int status;
+
+	if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
+		printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
+		       cmdlen, rxlen);
+		return -EINVAL;
+	}
+
+	reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+
+	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
+
+	/* 0 means 1 byte. */
+	reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
+		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
+	status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
+	if (status != 0)
+		return status;
+
+	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
+
+	/* Put the read value into rx_buf */
+	read_len = (rxlen > 4) ? 4 : rxlen;
+	memcpy(rxbuf, &reg, read_len);
+	rxbuf += read_len;
+
+	if (rxlen > 4) {
+		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
+
+		read_len = rxlen - read_len;
+		memcpy(rxbuf, &reg, read_len);
+	}
+	return 0;
+}
+
+/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
+int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
+	const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
+{
+	unsigned int reg = 0;
+	unsigned int addr_value;
+	unsigned int wr_data;
+	unsigned int wr_len;
+
+	if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
+		printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
+		       cmdlen, txlen);
+		return -EINVAL;
+	}
+
+	reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+
+	if (cmdlen == 4 || cmdlen == 5) {
+		/* Command with address */
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+		/* Number of bytes to write. */
+		reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
+			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
+		/* Get address */
+		addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
+			cmdlen >= 5 ? 4 : 3);
+
+		writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
+	}
+
+	if (txlen) {
+		/* writing data = yes */
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
+		reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
+			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
+
+		wr_len = txlen > 4 ? 4 : txlen;
+		memcpy(&wr_data, txbuf, wr_len);
+		writel(wr_data, reg_base +
+			CQSPI_REG_CMDWRITEDATALOWER);
+
+		if (txlen > 4) {
+			txbuf += wr_len;
+			wr_len = txlen - wr_len;
+			memcpy(&wr_data, txbuf, wr_len);
+			writel(wr_data, reg_base +
+				CQSPI_REG_CMDWRITEDATAUPPER);
+		}
+	}
+
+	/* Execute the command */
+	return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
+}
+
+/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
+int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
+	unsigned int cmdlen, const u8 *cmdbuf)
+{
+	unsigned int reg;
+	unsigned int rd_reg;
+	unsigned int addr_value;
+	unsigned int dummy_clk;
+	unsigned int dummy_bytes;
+	unsigned int addr_bytes;
+
+	/*
+	 * Identify addr_byte. All NOR flash device drivers are using fast read
+	 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
+	 * With that, the length is in value of 5 or 6. Only FRAM chip from
+	 * ramtron using normal read (which won't need dummy byte).
+	 * Unlikely NOR flash using normal read due to performance issue.
+	 */
+	if (cmdlen >= 5)
+		/* to cater fast read where cmd + addr + dummy */
+		addr_bytes = cmdlen - 2;
+	else
+		/* for normal read (only ramtron as of now) */
+		addr_bytes = cmdlen - 1;
+
+	/* Setup the indirect trigger address */
+	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+
+	/* Configure SRAM partition for read. */
+	writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
+	       CQSPI_REG_SRAMPARTITION);
+
+	/* Configure the opcode */
+	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+
+#if (CONFIG_SPI_FLASH_QUAD == 1)
+	/* Instruction and address at DQ0, data@DQ0-3. */
+	rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+#endif
+
+	/* Get address */
+	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
+	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+
+	/* The remaining lenght is dummy bytes. */
+	dummy_bytes = cmdlen - addr_bytes - 1;
+	if (dummy_bytes) {
+		if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
+			dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
+
+		rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
+#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
+		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
+#else
+		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
+#endif
+
+		/* Convert to clock cycles. */
+		dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
+		/* Need to minus the mode byte (8 clocks). */
+		dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
+
+		if (dummy_clk)
+			rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
+				<< CQSPI_REG_RD_INSTR_DUMMY_LSB;
+	}
+
+	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
+
+	/* set device size */
+	reg = readl(plat->regbase + CQSPI_REG_SIZE);
+	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
+	reg |= (addr_bytes - 1);
+	writel(reg, plat->regbase + CQSPI_REG_SIZE);
+	return 0;
+}
+
+int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+	unsigned int rxlen, u8 *rxbuf)
+{
+	unsigned int reg;
+
+	writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+
+	/* Start the indirect read transfer */
+	writel(CQSPI_REG_INDIRECTRD_START_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTRD);
+
+	if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
+				     (const void *)plat->ahbbase, rxlen))
+		goto failrd;
+
+	/* Check flash indirect controller */
+	reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
+	if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
+		reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
+		printf("QSPI: indirect completion status error with reg 0x%08x\n",
+		       reg);
+		goto failrd;
+	}
+
+	/* Clear indirect completion status */
+	writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTRD);
+	return 0;
+
+failrd:
+	/* Cancel the indirect read */
+	writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTRD);
+	return -1;
+}
+
+/* Opcode + Address (3/4 bytes) */
+int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
+	unsigned int cmdlen, const u8 *cmdbuf)
+{
+	unsigned int reg;
+	unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
+
+	if (cmdlen < 4 || cmdbuf == NULL) {
+		printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
+		       cmdlen, (unsigned int)cmdbuf);
+		return -EINVAL;
+	}
+	/* Setup the indirect trigger address */
+	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+
+	writel(CQSPI_REG_SRAM_PARTITION_WR,
+	       plat->regbase + CQSPI_REG_SRAMPARTITION);
+
+	/* Configure the opcode */
+	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
+
+	/* Setup write address. */
+	reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
+	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+
+	reg = readl(plat->regbase + CQSPI_REG_SIZE);
+	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
+	reg |= (addr_bytes - 1);
+	writel(reg, plat->regbase + CQSPI_REG_SIZE);
+	return 0;
+}
+
+int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+	unsigned int txlen, const u8 *txbuf)
+{
+	unsigned int reg = 0;
+	unsigned int retry;
+
+	/* Configure the indirect read transfer bytes */
+	writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
+
+	/* Start the indirect write transfer */
+	writel(CQSPI_REG_INDIRECTWR_START_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTWR);
+
+	if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
+		goto failwr;
+
+	/* Wait until last write is completed (FIFO empty) */
+	retry = CQSPI_REG_RETRY;
+	while (retry--) {
+		reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
+		if (reg == 0)
+			break;
+
+		udelay(1);
+	}
+
+	if (reg != 0) {
+		printf("QSPI: timeout for indirect write\n");
+		goto failwr;
+	}
+
+	/* Check flash indirect controller status */
+	retry = CQSPI_REG_RETRY;
+	while (retry--) {
+		reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
+		if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
+			break;
+		udelay(1);
+	}
+
+	if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
+		printf("QSPI: indirect completion status error with reg 0x%08x\n",
+		       reg);
+		goto failwr;
+	}
+
+	/* Clear indirect completion status */
+	writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTWR);
+	return 0;
+
+failwr:
+	/* Cancel the indirect write */
+	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
+	       plat->regbase + CQSPI_REG_INDIRECTWR);
+	return -1;
+}
+
+void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
+{
+	unsigned int reg;
+
+	/* enter XiP mode immediately and enable direct mode */
+	reg = readl(reg_base + CQSPI_REG_CONFIG);
+	reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+	reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
+	reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
+	writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+	/* keep the XiP mode */
+	writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
+
+	/* Enable mode bit at devrd */
+	reg = readl(reg_base + CQSPI_REG_RD_INSTR);
+	reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
+	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
+}
-- 
2.1.3

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Marek Vasut]

On Friday, November 07, 2014 at 12:37:49 PM, Stefan Roese wrote:

Hi!

> This driver is cloned from the Altera Rockerboard.org U-Boot
> repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
> modification to support the U-Boot driver model (DM).
> 
> As mentioned above, in this new version I ported this driver to the
> new driver model (DM). One big advantage of this move is that now
> multiple SPI drivers can be enabled on one platform. And since the
> SoCFPGA also has the Designware SPI master controller integrated,
> this feature is really needed to support both controllers.
> 
> Because of this, this series needs the DT support for SoCFPGA
> to be applied. For DT based probing in the SPI DM.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

[...]

> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> new file mode 100644
> index 0000000..c9a6142
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.h
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2012
> + * Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef __CADENCE_QSPI_H__
> +#define __CADENCE_QSPI_H__
> +
> +#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
> +
> +#define CQSPI_NO_DECODER_MAX_CS		4
> +#define CQSPI_DECODER_MAX_CS		16
> +#define CQSPI_READ_CAPTURE_MAX_DELAY	16
> +
> +struct cadence_spi_platdata {
> +	unsigned int	max_hz;
> +	void		*regbase;
> +	void		*ahbbase;
> +
> +	u32		page_size;
> +	u32		block_size;
> +	u32		tshsl_ns;
> +	u32		tsd2d_ns;
> +	u32		tchsh_ns;
> +	u32		tslch_ns;
> +};
> +
> +struct cadence_spi_priv {
> +	void		*regbase;
> +	void		*ahbbase;
> +	size_t		cmd_len;
> +	u8		cmd_buf[32];
> +	size_t		data_len;
> +
> +	int		qspi_is_init;
> +	unsigned int	qspi_calibrated_hz;
> +	unsigned int	qspi_calibrated_cs;
> +};
> +
> +/* Functions call declaration */
> +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
> +void cadence_qspi_apb_controller_enable(void *reg_base_addr);
> +void cadence_qspi_apb_controller_disable(void *reg_base_addr);

Is it really necessary to export all these functions ?

[...]

> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
> index 0000000..00a115f
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -0,0 +1,898 @@
> +/*
> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> met: + *  - Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer. + * 
> - Redistributions in binary form must reproduce the above copyright + *   
> notice, this list of conditions and the following disclaimer in the + *   
> documentation and/or other materials provided with the distribution. + * 
> - Neither the name of the Altera Corporation nor the
> + *    names of its contributors may be used to endorse or promote products
> + *    derived from this software without specific prior written
> permission. + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

This license is kinda iffy. What is this all about please ?

> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +#include "cadence_qspi.h"
> +
> +#define CQSPI_REG_POLL_US			(1) /* 1us */
> +#define CQSPI_REG_RETRY				(10000)
> +#define CQSPI_POLL_IDLE_RETRY			(3)
> +
> +#define CQSPI_FIFO_WIDTH			(4)

These braces around numbers should be fixed, but that's not the current pressing 
issue here.
[...]

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

Hi Dinh, Hi Vince!

a quick question for you:

On 07.11.2014 16:04, Marek Vasut wrote:

<snip>

>> diff --git a/drivers/spi/cadence_qspi_apb.c
>> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
>> index 0000000..00a115f
>> --- /dev/null
>> +++ b/drivers/spi/cadence_qspi_apb.c
>> @@ -0,0 +1,898 @@
>> +/*
>> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
>> + * All rights reserved.
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions are
>> met: + *  - Redistributions of source code must retain the above copyright
>> + *    notice, this list of conditions and the following disclaimer. + *
>> - Redistributions in binary form must reproduce the above copyright + *
>> notice, this list of conditions and the following disclaimer in the + *
>> documentation and/or other materials provided with the distribution. + *
>> - Neither the name of the Altera Corporation nor the
>> + *    names of its contributors may be used to endorse or promote products
>> + *    derived from this software without specific prior written
>> permission. + *
>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
>> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
>> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
>> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
>> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
>> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
>> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
>> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
>> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
>> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */
> 
> This license is kinda iffy. What is this all about please ?

Yes, I was wondering about this as well. And in the Linux kernel (Rocketboards)
this file is dual licensed. Here an extract:

<-------
/*
 * Driver for Cadence QSPI Controller
 *
 * Copyright (C) 2012 Altera Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */
<------

Could we not just use a "plain" GPL (v2) license here as well. Especially
since the other files in this driver are just normal GPL files.

Comments welcome.

Thanks,
Stefan

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Dinh Nguyen]

+CC: Graham Moore

On 11/07/2014 09:26 AM, Stefan Roese wrote:
> Hi Dinh, Hi Vince!
> 
> a quick question for you:
> 
> On 07.11.2014 16:04, Marek Vasut wrote:
> 
> <snip>
> 
>>> diff --git a/drivers/spi/cadence_qspi_apb.c
>>> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
>>> index 0000000..00a115f
>>> --- /dev/null
>>> +++ b/drivers/spi/cadence_qspi_apb.c
>>> @@ -0,0 +1,898 @@
>>> +/*
>>> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
>>> + * All rights reserved.
>>> + *
>>> + * Redistribution and use in source and binary forms, with or without
>>> + * modification, are permitted provided that the following conditions are
>>> met: + *  - Redistributions of source code must retain the above copyright
>>> + *    notice, this list of conditions and the following disclaimer. + *
>>> - Redistributions in binary form must reproduce the above copyright + *
>>> notice, this list of conditions and the following disclaimer in the + *
>>> documentation and/or other materials provided with the distribution. + *
>>> - Neither the name of the Altera Corporation nor the
>>> + *    names of its contributors may be used to endorse or promote products
>>> + *    derived from this software without specific prior written
>>> permission. + *
>>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
>>> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
>>> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
>>> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
>>> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>>> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
>>> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
>>> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
>>> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
>>> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
>>> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */
>>
>> This license is kinda iffy. What is this all about please ?
> 
> Yes, I was wondering about this as well. And in the Linux kernel (Rocketboards)
> this file is dual licensed. Here an extract:
> 
> <-------
> /*
>  * Driver for Cadence QSPI Controller
>  *
>  * Copyright (C) 2012 Altera Corporation
>  *
>  * This software is available to you under a choice of one of two
>  * licenses.  You may choose to be licensed under the terms of the GNU
>  * General Public License (GPL) Version 2, available from the file
>  * COPYING in the main directory of this source tree, or the
>  * OpenIB.org BSD license below:
>  *
>  *     Redistribution and use in source and binary forms, with or
>  *     without modification, are permitted provided that the following
>  *     conditions are met:
>  *
>  *      - Redistributions of source code must retain the above
>  *        copyright notice, this list of conditions and the following
>  *        disclaimer.
>  *
>  *      - Redistributions in binary form must reproduce the above
>  *        copyright notice, this list of conditions and the following
>  *        disclaimer in the documentation and/or other materials
>  *        provided with the distribution.
>  *
>  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
>  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>  * SOFTWARE.
>  *
>  */
> <------
> 
> Could we not just use a "plain" GPL (v2) license here as well. Especially
> since the other files in this driver are just normal GPL files.
> 
> Comments welcome.
> 

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Dinh

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

On 07.11.2014 20:56, Dinh Nguyen wrote:
> +CC: Graham Moore
>
> On 11/07/2014 09:26 AM, Stefan Roese wrote:
>> Hi Dinh, Hi Vince!

<snip>

>> Could we not just use a "plain" GPL (v2) license here as well. Especially
>> since the other files in this driver are just normal GPL files.
>>
>> Comments welcome.
>>
>
> Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.
>
> http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Interesting. Thanks for this info. But what is the implication of this 
new plain GPLv2'ed driver code to the current code in this patch (based 
on your Rocketboard.org version)?

Frankly, I really don't have time and motivation to re-port this new 
Linux version to U-Boot to get the GPLv2 version. How could we solve 
this?  Can you re-release this code under this new license (header)?

Thanks,
Stefan

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Marek Vasut]

On Saturday, November 08, 2014 at 01:18:31 PM, Stefan Roese wrote:
> On 07.11.2014 20:56, Dinh Nguyen wrote:
> > +CC: Graham Moore
> > 
> > On 11/07/2014 09:26 AM, Stefan Roese wrote:
> >> Hi Dinh, Hi Vince!
> 
> <snip>
> 
> >> Could we not just use a "plain" GPL (v2) license here as well.
> >> Especially since the other files in this driver are just normal GPL
> >> files.
> >> 
> >> Comments welcome.
> > 
> > Graham recent posted to lkml a patch series for QSPI that has a plain
> > GPLv2.
> > 
> > http://marc.info/?l=linux-kernel&m=141417788514196&w=2
> 
> Interesting. Thanks for this info. But what is the implication of this
> new plain GPLv2'ed driver code to the current code in this patch (based
> on your Rocketboard.org version)?
> 
> Frankly, I really don't have time and motivation to re-port this new
> Linux version to U-Boot to get the GPLv2 version. How could we solve
> this?  Can you re-release this code under this new license (header)?

Hi,

I have this one still marked as "Open Issue", any news here ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

On 06.12.2014 13:56, Marek Vasut wrote:
> On Saturday, November 08, 2014 at 01:18:31 PM, Stefan Roese wrote:
>> On 07.11.2014 20:56, Dinh Nguyen wrote:
>>> +CC: Graham Moore
>>>
>>> On 11/07/2014 09:26 AM, Stefan Roese wrote:
>>>> Hi Dinh, Hi Vince!
>>
>> <snip>
>>
>>>> Could we not just use a "plain" GPL (v2) license here as well.
>>>> Especially since the other files in this driver are just normal GPL
>>>> files.
>>>>
>>>> Comments welcome.
>>>
>>> Graham recent posted to lkml a patch series for QSPI that has a plain
>>> GPLv2.
>>>
>>> http://marc.info/?l=linux-kernel&m=141417788514196&w=2
>>
>> Interesting. Thanks for this info. But what is the implication of this
>> new plain GPLv2'ed driver code to the current code in this patch (based
>> on your Rocketboard.org version)?
>>
>> Frankly, I really don't have time and motivation to re-port this new
>> Linux version to U-Boot to get the GPLv2 version. How could we solve
>> this?  Can you re-release this code under this new license (header)?
>
> Hi,
>
> I have this one still marked as "Open Issue", any news here ?

Not from my side I'm afraid. Perhaps somebody from Altera (Dinh, 
Graham?) could chime in and let us know, if it would be possible to 
license the current QSPI file under GPL?

Thanks,
Stefan

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Marek Vasut]

On Monday, December 08, 2014 at 09:14:29 AM, Stefan Roese wrote:
> On 06.12.2014 13:56, Marek Vasut wrote:
> > On Saturday, November 08, 2014 at 01:18:31 PM, Stefan Roese wrote:
> >> On 07.11.2014 20:56, Dinh Nguyen wrote:
> >>> +CC: Graham Moore
> >>> 
> >>> On 11/07/2014 09:26 AM, Stefan Roese wrote:
> >>>> Hi Dinh, Hi Vince!
> >> 
> >> <snip>
> >> 
> >>>> Could we not just use a "plain" GPL (v2) license here as well.
> >>>> Especially since the other files in this driver are just normal GPL
> >>>> files.
> >>>> 
> >>>> Comments welcome.
> >>> 
> >>> Graham recent posted to lkml a patch series for QSPI that has a plain
> >>> GPLv2.
> >>> 
> >>> http://marc.info/?l=linux-kernel&m=141417788514196&w=2
> >> 
> >> Interesting. Thanks for this info. But what is the implication of this
> >> new plain GPLv2'ed driver code to the current code in this patch (based
> >> on your Rocketboard.org version)?
> >> 
> >> Frankly, I really don't have time and motivation to re-port this new
> >> Linux version to U-Boot to get the GPLv2 version. How could we solve
> >> this?  Can you re-release this code under this new license (header)?
> > 
> > Hi,
> > 
> > I have this one still marked as "Open Issue", any news here ?
> 
> Not from my side I'm afraid. Perhaps somebody from Altera (Dinh,
> Graham?) could chime in and let us know, if it would be possible to
> license the current QSPI file under GPL?

Is anyone planning to take up the task of porting the V10 of the QSPI driver
into U-Boot to replace the current horror ? ;-)

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Simon Glass]

Hi Stefan,

On 7 November 2014 04:37, Stefan Roese <sr@denx.de> wrote:
>
> This driver is cloned from the Altera Rockerboard.org U-Boot
> repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
> modification to support the U-Boot driver model (DM).
>
> As mentioned above, in this new version I ported this driver to the
> new driver model (DM). One big advantage of this move is that now
> multiple SPI drivers can be enabled on one platform. And since the
> SoCFPGA also has the Designware SPI master controller integrated,
> this feature is really needed to support both controllers.
>
> Because of this, this series needs the DT support for SoCFPGA
> to be applied. For DT based probing in the SPI DM.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>


For the driver model parts:

Reviewed-by: Simon Glass <sjg@chromium.org>

(tiny nit below if you reissue)

>
> ---
> v4:
> - Reworked to support driver model (DM)
> - Coding-style changes to make it checkpatch clean
>
> v3:
> - Added SPDX License Indentifier
> - Removed CQSPI_WRITEL / CQSPI_READL
>
>  drivers/spi/Makefile           |   1 +
>  drivers/spi/cadence_qspi.c     | 345 ++++++++++++++++
>  drivers/spi/cadence_qspi.h     |  76 ++++
>  drivers/spi/cadence_qspi_apb.c | 898 +++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 1320 insertions(+)
>  create mode 100644 drivers/spi/cadence_qspi.c
>  create mode 100644 drivers/spi/cadence_qspi.h
>  create mode 100644 drivers/spi/cadence_qspi_apb.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index eabbf27..964fdc1 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
>  obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
> +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>  obj-$(CONFIG_CF_SPI) += cf_spi.o
>  obj-$(CONFIG_CF_QSPI) += cf_qspi.o
>  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> new file mode 100644
> index 0000000..fa95b19
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.c
> @@ -0,0 +1,345 @@
> +/*
> + * Copyright (C) 2012
> + * Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/errno.h>
> +#include "cadence_qspi.h"
> +
> +#define CQSPI_STIG_READ                        0
> +#define CQSPI_STIG_WRITE               1
> +#define CQSPI_INDIRECT_READ            2
> +#define CQSPI_INDIRECT_WRITE           3
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static int cadence_spi_write_speed(struct udevice *bus, uint hz)
> +{
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +
> +       cadence_qspi_apb_config_baudrate_div(priv->regbase,
> +                                            CONFIG_CQSPI_REF_CLK, hz);
> +
> +       /* Reconfigure delay timing if speed is changed. */
> +       cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
> +                              plat->tshsl_ns, plat->tsd2d_ns,
> +                              plat->tchsh_ns, plat->tslch_ns);
> +
> +       return 0;
> +}
> +
> +/* Calibration sequence to determine the read data capture delay register */
> +static int spi_calibration(struct udevice *bus)
> +{
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +       void *base = priv->regbase;
> +       u8 opcode_rdid = 0x9F;
> +       unsigned int idcode = 0, temp = 0;
> +       int err = 0, i, range_lo = -1, range_hi = -1;
> +
> +       /* start with slowest clock (1 MHz) */
> +       cadence_spi_write_speed(bus, 1000000);
> +
> +       /* configure the read data capture delay register to 0 */
> +       cadence_qspi_apb_readdata_capture(base, 1, 0);
> +
> +       /* Enable QSPI */
> +       cadence_qspi_apb_controller_enable(base);
> +
> +       /* read the ID which will be our golden value */
> +       err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
> +               3, (u8 *)&idcode);
> +       if (err) {
> +               puts("SF: Calibration failed (read)\n");
> +               return err;
> +       }
> +
> +       /* use back the intended clock and find low range */
> +       cadence_spi_write_speed(bus, plat->max_hz);
> +       for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
> +               /* Disable QSPI */
> +               cadence_qspi_apb_controller_disable(base);
> +
> +               /* reconfigure the read data capture delay register */
> +               cadence_qspi_apb_readdata_capture(base, 1, i);
> +
> +               /* Enable back QSPI */
> +               cadence_qspi_apb_controller_enable(base);
> +
> +               /* issue a RDID to get the ID value */
> +               err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
> +                       3, (u8 *)&temp);
> +               if (err) {
> +                       puts("SF: Calibration failed (read)\n");
> +                       return err;
> +               }
> +
> +               /* search for range lo */
> +               if (range_lo == -1 && temp == idcode) {
> +                       range_lo = i;
> +                       continue;
> +               }
> +
> +               /* search for range hi */
> +               if (range_lo != -1 && temp != idcode) {
> +                       range_hi = i - 1;
> +                       break;
> +               }
> +               range_hi = i;
> +       }
> +
> +       if (range_lo == -1) {
> +               puts("SF: Calibration failed (low range)\n");
> +               return err;
> +       }
> +
> +       /* Disable QSPI for subsequent initialization */
> +       cadence_qspi_apb_controller_disable(base);
> +
> +       /* configure the final value for read data capture delay register */
> +       cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
> +       debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
> +             (range_hi + range_lo) / 2, range_lo, range_hi);
> +
> +       /* just to ensure we do once only when speed or chip select change */
> +       priv->qspi_calibrated_hz = plat->max_hz;
> +       priv->qspi_calibrated_cs = spi_chip_select(bus);
> +
> +       return 0;
> +}
> +
> +static int cadence_spi_set_speed(struct udevice *bus, uint hz)
> +{
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +       int err;
> +
> +       /* Disable QSPI */
> +       cadence_qspi_apb_controller_disable(priv->regbase);
> +
> +       cadence_spi_write_speed(bus, hz);
> +
> +       /* Calibration required for different SCLK speed or chip select */
> +       if (priv->qspi_calibrated_hz != plat->max_hz ||
> +           priv->qspi_calibrated_cs != spi_chip_select(bus)) {
> +               err = spi_calibration(bus);
> +               if (err)
> +                       return err;
> +       }
> +
> +       /* Enable QSPI */
> +       cadence_qspi_apb_controller_enable(priv->regbase);
> +
> +       debug("%s: speed=%d\n", __func__, hz);
> +
> +       return 0;
> +}
> +
> +static int cadence_spi_probe(struct udevice *bus)
> +{
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +
> +       priv->regbase = plat->regbase;
> +       priv->ahbbase = plat->ahbbase;
> +
> +       if (!priv->qspi_is_init) {
> +               cadence_qspi_apb_controller_init(plat);
> +               priv->qspi_is_init = 1;
> +       }
> +
> +       return 0;
> +}
> +
> +static int cadence_spi_set_mode(struct udevice *bus, uint mode)
> +{
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +       unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
> +       unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
> +
> +       /* Disable QSPI */
> +       cadence_qspi_apb_controller_disable(priv->regbase);
> +
> +       /* Set SPI mode */
> +       cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
> +
> +       /* Enable QSPI */
> +       cadence_qspi_apb_controller_enable(priv->regbase);
> +
> +       return 0;
> +}
> +
> +static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
> +                           const void *dout, void *din, unsigned long flags)
> +{
> +       struct udevice *bus = dev->parent;
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       struct cadence_spi_priv *priv = dev_get_priv(bus);
> +       void *base = priv->regbase;
> +       u8 *cmd_buf = priv->cmd_buf;
> +       size_t data_bytes;
> +       int err = 0;
> +       u32 mode = CQSPI_STIG_WRITE;
> +
> +       if (flags & SPI_XFER_BEGIN) {
> +               /* copy command to local buffer */
> +               priv->cmd_len = bitlen / 8;
> +               memcpy(cmd_buf, dout, priv->cmd_len);
> +       }
> +
> +       if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
> +               /* if start and end bit are set, the data bytes is 0. */
> +               data_bytes = 0;
> +       } else {
> +               data_bytes = bitlen / 8;
> +       }
> +       debug("%s: len=%d [bytes]\n", __func__, data_bytes);
> +
> +       /* Set Chip select */
> +       cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
> +                                   CONFIG_CQSPI_DECODER);
> +
> +       if ((flags & SPI_XFER_END) || (flags == 0)) {
> +               if (priv->cmd_len == 0) {
> +                       printf("QSPI: Error, command is empty.\n");
> +                       return -1;
> +               }
> +
> +               if (din && data_bytes) {
> +                       /* read */
> +                       /* Use STIG if no address. */
> +                       if (!CQSPI_IS_ADDR(priv->cmd_len))
> +                               mode = CQSPI_STIG_READ;
> +                       else
> +                               mode = CQSPI_INDIRECT_READ;
> +               } else if (dout && !(flags & SPI_XFER_BEGIN)) {
> +                       /* write */
> +                       if (!CQSPI_IS_ADDR(priv->cmd_len))
> +                               mode = CQSPI_STIG_WRITE;
> +                       else
> +                               mode = CQSPI_INDIRECT_WRITE;
> +               }
> +
> +               switch (mode) {
> +               case CQSPI_STIG_READ:
> +                       err = cadence_qspi_apb_command_read(
> +                               base, priv->cmd_len, cmd_buf,
> +                               data_bytes, din);
> +
> +               break;
> +               case CQSPI_STIG_WRITE:
> +                       err = cadence_qspi_apb_command_write(base,
> +                               priv->cmd_len, cmd_buf,
> +                               data_bytes, dout);
> +               break;
> +               case CQSPI_INDIRECT_READ:
> +                       err = cadence_qspi_apb_indirect_read_setup(plat,
> +                               priv->cmd_len, cmd_buf);
> +                       if (!err) {
> +                               err = cadence_qspi_apb_indirect_read_execute
> +                               (plat, data_bytes, din);
> +                       }
> +               break;
> +               case CQSPI_INDIRECT_WRITE:
> +                       err = cadence_qspi_apb_indirect_write_setup
> +                               (plat, priv->cmd_len, cmd_buf);
> +                       if (!err) {
> +                               err = cadence_qspi_apb_indirect_write_execute
> +                               (plat, data_bytes, dout);
> +                       }
> +               break;
> +               default:
> +                       err = -1;
> +                       break;
> +               }
> +
> +               if (flags & SPI_XFER_END) {
> +                       /* clear command buffer */
> +                       memset(cmd_buf, 0, sizeof(priv->cmd_buf));
> +                       priv->cmd_len = 0;
> +               }
> +       }
> +
> +       return err;
> +}
> +
> +static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
> +{
> +       struct cadence_spi_platdata *plat = bus->platdata;
> +       const void *blob = gd->fdt_blob;
> +       int node = bus->of_offset;
> +       int subnode;
> +       u32 data[4];
> +       int ret;
> +
> +       /* 2 base addresses are needed, lets get them from the DT */
> +       ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
> +       if (ret) {
> +               printf("Error: Can't get base addresses (ret=%d)!\n", ret);
> +               return -ENODEV;
> +       }
> +
> +       plat->regbase = (void *)data[0];
> +       plat->ahbbase = (void *)data[2];
> +
> +       /* Use 500KHz as a suitable default */
> +       plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> +                                     500000);
> +
> +       /* All other paramters are embedded in the child node */
> +       subnode = fdt_first_subnode(blob, node);
> +       if (!subnode) {
> +               printf("Error: subnode with SPI flash config missing!\n");
> +               return -ENODEV;

Maybe -EINVAL for these two? I feel that ENODEV should be for when
there really is no device.

Regards,
Simon

[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Stefan Roese]

This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
 arch/arm/dts/socfpga.dtsi                  | 15 +++++++++++++++
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4472fd9..4a789a9 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,21 @@
 			clock-names = "biu", "ciu";
 		};
 
+		qspi: spi at ff705000 {
+			compatible = "cadence,qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xff705000 0x1000>,
+				<0xffa00000 0x1000>;
+			interrupts = <0 151 4>;
+			clocks = <&qspi_clk>;
+			ext-decoder = <0>;  /* external decoder */
+			num-chipselect = <4>;
+			fifo-depth = <128>;
+			bus-num = <2>;
+			status = "disabled";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index a1814b4..9277174 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -48,3 +48,23 @@
 &mmc {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
-- 
2.1.3

[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Simon Glass]

Hi Stefan,

On 7 November 2014 04:37, Stefan Roese <sr@denx.de> wrote:
> This DT node is taken from the Rocketboard.org Linux repsitory. And
> is needed to enable (configure) the Cadence DM SPI driver.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> ---
>  arch/arm/dts/socfpga.dtsi                  | 15 +++++++++++++++
>  arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++
>  2 files changed, 35 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 4472fd9..4a789a9 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -639,6 +639,21 @@
>                         clock-names = "biu", "ciu";
>                 };
>
> +               qspi: spi at ff705000 {
> +                       compatible = "cadence,qspi";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xff705000 0x1000>,
> +                               <0xffa00000 0x1000>;
> +                       interrupts = <0 151 4>;
> +                       clocks = <&qspi_clk>;
> +                       ext-decoder = <0>;  /* external decoder */
> +                       num-chipselect = <4>;
> +                       fifo-depth = <128>;
> +                       bus-num = <2>;
> +                       status = "disabled";
> +               };
> +

Is this the same binding as Linux? Can you please bring in the binding
document too? Some of these feel like they should have a
"manufacture," prefix.


>                 /* Local timer */
>                 timer at fffec600 {
>                         compatible = "arm,cortex-a9-twd-timer";
> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> index a1814b4..9277174 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> @@ -48,3 +48,23 @@
>  &mmc {
>         status = "okay";
>  };
> +
> +&qspi {
> +       status = "okay";
> +
> +       flash0: n25q00 at 0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "n25q00";
> +               reg = <0>;      /* chip select */
> +               spi-max-frequency = <50000000>;
> +               m25p,fast-read;
> +               page-size = <256>;
> +               block-size = <16>; /* 2^16, 64KB */
> +               read-delay = <4>;  /* delay value in read data capture register */
> +               tshsl-ns = <50>;
> +               tsd2d-ns = <50>;
> +               tchsh-ns = <4>;
> +               tslch-ns = <4>;
> +       };
> +};
> --
> 2.1.3
>

Regards,
Simon

[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Stefan Roese]

Hi Simon,

On 07.11.2014 18:21, Simon Glass wrote:
>> +               qspi: spi at ff705000 {
>> +                       compatible = "cadence,qspi";
>> +                       #address-cells = <1>;
>> +                       #size-cells = <0>;
>> +                       reg = <0xff705000 0x1000>,
>> +                               <0xffa00000 0x1000>;
>> +                       interrupts = <0 151 4>;
>> +                       clocks = <&qspi_clk>;
>> +                       ext-decoder = <0>;  /* external decoder */
>> +                       num-chipselect = <4>;
>> +                       fifo-depth = <128>;
>> +                       bus-num = <2>;
>> +                       status = "disabled";
>> +               };
>> +
>
> Is this the same binding as Linux? Can you please bring in the binding
> document too? Some of these feel like they should have a
> "manufacture," prefix.

Yes, its from Linux. But not from kernel.org but from the Altera 
Rocketboards.org version (v3.16). So the bindings might change if this 
driver would be pushed to mainline Linux.

Sure, I can include the binding document as well. Good idea.

Thanks,
Stefan

[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Pavel Machek]

On Fri 2014-11-07 18:26:05, Stefan Roese wrote:
> Hi Simon,
> 
> On 07.11.2014 18:21, Simon Glass wrote:
> >>+               qspi: spi at ff705000 {
> >>+                       compatible = "cadence,qspi";
> >>+                       #address-cells = <1>;
> >>+                       #size-cells = <0>;
> >>+                       reg = <0xff705000 0x1000>,
> >>+                               <0xffa00000 0x1000>;
> >>+                       interrupts = <0 151 4>;
> >>+                       clocks = <&qspi_clk>;
> >>+                       ext-decoder = <0>;  /* external decoder */
> >>+                       num-chipselect = <4>;
> >>+                       fifo-depth = <128>;
> >>+                       bus-num = <2>;
> >>+                       status = "disabled";
> >>+               };
> >>+
> >
> >Is this the same binding as Linux? Can you please bring in the binding
> >document too? Some of these feel like they should have a
> >"manufacture," prefix.
> 
> Yes, its from Linux. But not from kernel.org but from the Altera
> Rocketboards.org version (v3.16). So the bindings might change if this
> driver would be pushed to mainline Linux.

I guess it would be good to submit the binding to Linux for review, so
that we don't end up with two incompatible bindings...

								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Dinh Nguyen]

+CC: Graham Moore

On 11/10/2014 04:47 AM, Pavel Machek wrote:
> On Fri 2014-11-07 18:26:05, Stefan Roese wrote:
>> Hi Simon,
>>
>> On 07.11.2014 18:21, Simon Glass wrote:
>>>> +               qspi: spi at ff705000 {
>>>> +                       compatible = "cadence,qspi";
>>>> +                       #address-cells = <1>;
>>>> +                       #size-cells = <0>;
>>>> +                       reg = <0xff705000 0x1000>,
>>>> +                               <0xffa00000 0x1000>;
>>>> +                       interrupts = <0 151 4>;
>>>> +                       clocks = <&qspi_clk>;
>>>> +                       ext-decoder = <0>;  /* external decoder */
>>>> +                       num-chipselect = <4>;
>>>> +                       fifo-depth = <128>;
>>>> +                       bus-num = <2>;
>>>> +                       status = "disabled";
>>>> +               };
>>>> +
>>>
>>> Is this the same binding as Linux? Can you please bring in the binding
>>> document too? Some of these feel like they should have a
>>> "manufacture," prefix.
>>
>> Yes, its from Linux. But not from kernel.org but from the Altera
>> Rocketboards.org version (v3.16). So the bindings might change if this
>> driver would be pushed to mainline Linux.
> 
> I guess it would be good to submit the binding to Linux for review, so
> that we don't end up with two incompatible bindings...
> 

Graham has already submitted an RFC, but have not gotten any feedback yet.

http://marc.info/?l=linux-kernel&m=141417787314186&w=2

[U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Stefan Roese]

Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 9277174..02bb8b3 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -25,6 +25,10 @@
 		bootargs = "console=ttyS0,115200";
 	};
 
+ 	aliases {
+		spi0 = "/spi at ff705000";		/* QSPI */
+ 	};
+
 	memory {
 		name = "memory";
 		device_type = "memory";
-- 
2.1.3

[U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Marek Vasut]

On Friday, November 07, 2014 at 12:37:51 PM, Stefan Roese wrote:
> Without this alias, DM based probing does not work. So lets add this
> alias to get the bus numbering correct.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Just a really minor nit, while picking those patches into a temporary branch so 
they don't get lost, I see this.

Applying: arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
/work/U-Boot/upstream/u-boot-socfpga/.git/rebase-apply/patch:13: space before 
tab in indent.
        aliases {
/work/U-Boot/upstream/u-boot-socfpga/.git/rebase-apply/patch:15: space before 
tab in indent.
        };
warning: 2 lines add whitespace errors.

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Simon Glass]

On 7 November 2014 04:37, Stefan Roese <sr@denx.de> wrote:
> Without this alias, DM based probing does not work. So lets add this
> alias to get the bus numbering correct.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/4 v4] arm: socfpga: Add Cadence QSPI support to config header

[Stefan Roese]

With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
v4:
- Some config parameters (page-size and timing are now removed
  and will be read from the DT instead)

 include/configs/socfpga_common.h | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f7b314d..9fc4212 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -141,7 +141,7 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
 #endif
 
- /*
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -169,6 +169,29 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #define CONFIG_CMD_I2C
 
 /*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL	/* QSPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH		/* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO	/* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION	/* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER		0
+#define CONFIG_CMD_SF
+#endif
+
+/*
  * Serial Driver
  */
 #define CONFIG_SYS_NS16550
-- 
2.1.3