[U-Boot] [PATCH] arm: cache: Implement cache range check for v7

From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: cache: Implement cache range check for v7
Date: Mon, 25 Jan 2016 11:04:59 -0500	[thread overview]
Message-ID: <20160125160459.GJ3359@bill-the-cat> (raw)
In-Reply-To: <201601241828.12351.marex@denx.de>

On Sun, Jan 24, 2016 at 06:28:12PM +0100, Marek Vasut wrote:
> On Monday, December 28, 2015 at 04:23:46 PM, Marek Vasut wrote:
> > On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote:
> > > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote:
> > > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote:
> > > > > Add code to aid tracking down cache alignment issues.
> > > > > In case DEBUG is defined in the cache.c, this code will
> > > > > check alignment of each attempt to flush/invalidate data
> > > > > cache and print a warning if the alignment is incorrect.
> > > > > If DEBUG is not defined, this code is optimized out.
> > > > > 
> > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > > > > Cc: Tom Rini <trini@konsulko.com>
> > > > 
> > > > Bump ?
> > > 
> > > Bump ?
> > 
> > Bump #3 ?
> 
> Bump #4 ?

Albert?

> > > > >  arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
> > > > >  1 file changed, 21 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm/cpu/armv7/cache_v7.c
> > > > > b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644
> > > > > --- a/arch/arm/cpu/armv7/cache_v7.c
> > > > > +++ b/arch/arm/cpu/armv7/cache_v7.c
> > > > > @@ -16,6 +16,23 @@
> > > > > 
> > > > >  #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
> > > > >  
> > > > >  #ifndef CONFIG_SYS_DCACHE_OFF
> > > > > 
> > > > > +static int check_cache_range(unsigned long start, unsigned long
> > > > > stop) +{
> > > > > +	int ok = 1;
> > > > > +
> > > > > +	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> > > > > +		ok = 0;
> > > > > +
> > > > > +	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> > > > > +		ok = 0;
> > > > > +
> > > > > +	if (!ok)
> > > > > +		debug("CACHE: Misaligned operation at range [%08lx, 
> %08lx]\n",
> > > > > +			start, stop);
> > > > > +
> > > > > +	return ok;
> > > > > +}
> > > > > +
> > > > > 
> > > > >  /*
> > > > >  
> > > > >   * Write the level and type you want to Cache Size Selection
> > > > > 
> > > > > Register(CSSELR) * to get size details from Current Cache Size ID
> > > > > Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)
> > > > > 
> > > > >   */
> > > > >  
> > > > >  void invalidate_dcache_range(unsigned long start, unsigned long
> > > > >  stop) {
> > > > > 
> > > > > +	check_cache_range(start, stop);
> > > > > +
> > > > > 
> > > > >  	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
> > > > >  	
> > > > >  	v7_outer_cache_inval_range(start, stop);
> > > > > 
> > > > > @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,
> > > > > unsigned long stop) */
> > > > > 
> > > > >  void flush_dcache_range(unsigned long start, unsigned long stop)
> > > > >  {
> > > > > 
> > > > > +	check_cache_range(start, stop);
> > > > > +
> > > > > 
> > > > >  	v7_dcache_maint_range(start, stop, 
> ARMV7_DCACHE_CLEAN_INVAL_RANGE);
> > > > >  	
> > > > >  	v7_outer_cache_flush_range(start, stop);
> > > > 
> > > > Best regards,
> > > > Marek Vasut
> > 
> > Best regards,
> > Marek Vasut
> 
> Best regards,
> Marek Vasut
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

-- 
Tom
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