From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Mon, 25 Jan 2016 22:22:07 +0100
Subject: [U-Boot] [PATCH] arm: cache: Implement cache range check for v7
In-Reply-To: <20160125160459.GJ3359@bill-the-cat>
References: <1438029257-8255-1-git-send-email-marex@denx.de>
 <201512110536.15139.marex@denx.de>
 <201512281623.46851.marex@denx.de>
 <201601241828.12351.marex@denx.de>
 <20160125160459.GJ3359@bill-the-cat>
Message-ID: <20160125222207.5dc3bd6e@lilith>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hello Tom,

On Mon, 25 Jan 2016 11:04:59 -0500, Tom Rini <trini@konsulko.com> wrote:
> On Sun, Jan 24, 2016 at 06:28:12PM +0100, Marek Vasut wrote:
> > On Monday, December 28, 2015 at 04:23:46 PM, Marek Vasut wrote:
> > > On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote:
> > > > On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote:
> > > > > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote:
> > > > > > Add code to aid tracking down cache alignment issues.
> > > > > > In case DEBUG is defined in the cache.c, this code will
> > > > > > check alignment of each attempt to flush/invalidate data
> > > > > > cache and print a warning if the alignment is incorrect.
> > > > > > If DEBUG is not defined, this code is optimized out.
> > > > > > 
> > > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > > > > > Cc: Tom Rini <trini@konsulko.com>
> > > > > 
> > > > > Bump ?
> > > > 
> > > > Bump ?
> > > 
> > > Bump #3 ?
> > 
> > Bump #4 ?
> 
> Albert?

Sorry. Applied to u-boot-arm/master, thanks.

Amicalement,
-- 
Albert.