From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 26 Jan 2016 21:29:09 -0500 Subject: [U-Boot] [PATCH] armv7: add cacheline sizes where missing In-Reply-To: <1453826449-14346-1-git-send-email-albert.u.boot@aribaud.net> References: <1453826449-14346-1-git-send-email-albert.u.boot@aribaud.net> Message-ID: <20160127022909.GO426@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Jan 26, 2016 at 05:40:49PM +0100, Albert ARIBAUD wrote: > Some armv7 targets are missing a cache line size declaration. > In preparation for "arm: cache: Implement cache range check for v7" > patch, add these declarations with the appropriate value for > the target's SoC or CPU. > > Signed-off-by: Albert ARIBAUD For the TI boards: Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: