From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Jan 2016 05:10:59 +0100
Subject: [U-Boot] [PATCH] armv7: add cacheline sizes where missing
In-Reply-To: <1453826449-14346-1-git-send-email-albert.u.boot@aribaud.net>
References: <1453826449-14346-1-git-send-email-albert.u.boot@aribaud.net>
Message-ID: <201601270510.59784.marex@denx.de>
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To: u-boot@lists.denx.de

On Tuesday, January 26, 2016 at 05:40:49 PM, Albert ARIBAUD wrote:
> Some armv7 targets are missing a cache line size declaration.
> In preparation for "arm: cache: Implement cache range check for v7"
> patch, add these declarations with the appropriate value for
> the target's SoC or CPU.
> 
> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

[...]

> diff --git a/include/configs/at91-sama5_common.h
> b/include/configs/at91-sama5_common.h index 9db4a4f..7b06601 100644
> --- a/include/configs/at91-sama5_common.h
> +++ b/include/configs/at91-sama5_common.h
> @@ -12,6 +12,8 @@
> 
>  #include <asm/hardware.h>
> 
> +#define CONFIG_SYS_CACHELINE_SIZE	64
> +
>  #define CONFIG_SYS_TEXT_BASE		0x26f00000
> 
>  /* ARM asynchronous clock */

I think SAMA5 is CortexA5 and that has 32B cachelines.

Best regards,
Marek Vasut