From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 27 Jan 2016 23:07:57 +0100 Subject: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew In-Reply-To: <1453931160-32264-2-git-send-email-dinguyen@opensource.altera.com> References: <1453931160-32264-1-git-send-email-dinguyen@opensource.altera.com> <1453931160-32264-2-git-send-email-dinguyen@opensource.altera.com> Message-ID: <201601272307.57574.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wednesday, January 27, 2016 at 10:46:00 PM, dinguyen at opensource.altera.com wrote: > From: Dinh Nguyen > > The picoseconds to register value divisor(ps_to_regval) should be 60 and > not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the > correct divisor because the 4-bit skew values are defined from > 0x0000(-420ps) to 0xffff(480ps), increments of 60. > > For example, a DTS skew value of 420, represents 0ps delay, which should be > 0x7. With the previous divisor of 200, it would result in 0x2, which > represents a -300ps delay. > > With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with > 1Gb ethernet. > > References: > http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 > > Signed-off-by: Dinh Nguyen This is fine, thanks for spotting it. Acked-by: Marek Vasut Joe, will you pick these two and push for 2016.03 or shall I pick them ? Best regards, Marek Vasut