From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Thu, 28 Jan 2016 10:03:04 +0100 Subject: [U-Boot] [PATCH v2] armv7: add cacheline sizes where missing In-Reply-To: <1453880771-22742-1-git-send-email-albert.u.boot@aribaud.net> References: <1453880771-22742-1-git-send-email-albert.u.boot@aribaud.net> Message-ID: <20160128100304.3ad0d196@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, 27 Jan 2016 08:46:11 +0100, Albert ARIBAUD wrote: > Some armv7 targets are missing a cache line size declaration. > In preparation for "arm: cache: Implement cache range check for v7" > patch, add these declarations with the appropriate value for > the target's SoC or CPU. > > Signed-off-by: Albert ARIBAUD > --- > > Changes in v2: > - fix include/configs/at91-sama5_common.h (Cortex-A5: 32 bytes) Absent any complaint today, I will apply this as a prerequisite for Marek's "arm: cache: Implement cache range check for v7". Amicalement, -- Albert.