[U-Boot] [PATCH 1/2] arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hello Marek,

On Tue, 29 Dec 2015 19:44:01 +0100, Marek Vasut <marex@denx.de> wrote:
> The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
> set, it configures TTBR0 register. This register must be configured for the
> cache on ARMv7 to operate correctly.
> 
> The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
> TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
> issues which are hard to replicate, for example certain USB sticks are not
> detected or QSPI NOR sometimes fails to write pages completely.
> 
> The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
> correct because the code which added the test(s) for CONFIG_ARMV7 was added
> shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
> not adjusted correctly to reflect that change.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Simon Glass <sjg@chromium.org>
> ---
>  arch/arm/include/asm/system.h | 4 ++--
>  arch/arm/lib/cache-cp15.c     | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index 71b3108..dec83c7 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -220,7 +220,7 @@ static inline void set_dacr(unsigned int val)
>  	isb();
>  }
>  
> -#ifdef CONFIG_ARMV7
> +#ifdef CONFIG_CPU_V7
>  /* Short-Descriptor Translation Table Level 1 Bits */
>  #define TTB_SECT_NS_MASK	(1 << 19)
>  #define TTB_SECT_NG_MASK	(1 << 17)
> @@ -257,7 +257,7 @@ enum {
>  	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
>  };
>  
> -#ifdef CONFIG_ARMV7
> +#ifdef CONFIG_CPU_V7
>  /* TTBR0 bits */
>  #define TTBR0_BASE_ADDR_MASK	0xFFFFC000
>  #define TTBR0_RGN_NC			(0 << 3)
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index c65e068..8e18538 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -96,7 +96,7 @@ static inline void mmu_setup(void)
>  		dram_bank_mmu_setup(i);
>  	}
>  
> -#ifdef CONFIG_ARMV7
> +#ifdef CONFIG_CPU_V7
>  	/* Set TTBR0 */
>  	reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
>  #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
> -- 
> 2.1.4
> 

Series applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.